11.4.3. Performance Monitor Common Event Identification Register 0

The PMCEID0 characteristics are:

Purpose

Defines which common architectural and common micro-architectural feature events are implemented.

Usage constraints

The PMCEID0 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Accessible in Hyp mode and all modes executing at PL1 when HDCR.TPM is set to 0.

  • Accessible in User mode only when PMUSERENR.EN is set to 1 and HDCR.TPM is set to 0.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 11.1.

Table 11.4 shows the PMCEID0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0.

PMCEID1[31:0] is reserved.

Table 11.4. Common Event Identification Register 0 bit assignments

BitEvent numberEvent implemented if set to 1 or not implemented if set to 0
[31]0x1FReserved.
[30]0x1E
[29]0x1DBus cycle. This event is implemented.
[28]0x1CInstruction architecturally executed, condition check pass, write to translation table base. This event is implemented.
[27]0x1BInstruction speculatively executed. This event is implemented.
[26]0x1ALocal memory error. This event is implemented.
[25]0x19Bus access. This event is implemented.
[24]0x18Level 2 data cache write-back. This event is implemented.
[23]0x17Level 2 data cache refill. This event is implemented.
[22]0x16Level 2 data cache access. This event is implemented.
[21]0x15Level 1 data cache write-back. This event is implemented.
[20]0x14Level 1 instruction cache access. This event is implemented.
[19]0x13Data memory access. This event is implemented.
[18]0x12Predictable branch speculatively executed. This bit is RAO.
[17]0x11Cycle, this bit is RAO.
[16]0x10Mispredicted or not predicted branch speculatively executed. This bit is RAO.
[15]0x0FInstruction architecturally executed, condition check pass, unaligned load or store. This event is not implemented.
[14]0x0EInstruction architecturally executed, condition check pass, procedure return. This event is not implemented.
[13]0x0DInstruction architecturally executed, immediate branch. This event is not implemented.
[12]0x0CInstruction architecturally executed, condition check pass, software change of the PC. This event is not implemented.
[11]0x0BInstruction architecturally executed, condition check pass, write to CONTEXTIDR. This event is implemented.
[10]0x0AInstruction architecturally executed, condition check pass, exception return. This event is implemented.
[9]0x09Exception taken. This event is implemented.
[8]0x08Instruction architecturally executed, this bit is RAO.
[7]0x07Instruction architecturally executed, condition check pass, store. This event is not implemented.
[6]0x06Instruction architecturally executed, condition check pass, load. This event is not implemented.
[5]0x05Level 1 data TLB refill. This event is implemented.
[4]0x04Level 1 data cache access. This bit is RAO.
[3]0x03Level 1 data cache refill. This bit is RAO.
[2]0x02Level 1 instruction TLB refill. This event is implemented.
[1]0x01Level 1 instruction cache refill. This event is implemented.
[0]0x00Instruction architecturally executed, condition check pass, software increment. This bit is RAO.

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