The L1 instruction TLB is a 32-entry fully-associative structure. This TLB caches entries at the 4KB granularity of Virtual Address (VA) to Physical Address (PA) mapping only. If the page tables map the memory region to a larger granularity than 4K, it only allocates one mapping for the particular 4K region to which the current access corresponds.

A hit in the instruction TLB provides a single CLK cycle access to the translation, and returns the physical address to the instruction cache for comparison. It also checks the access permissions to signal a Prefetch Abort.