Cortex-A15 MPCore Technical Reference Manual: 5.1. About the MMU

5.1. About the MMU

The Cortex-A15 MPCore processor implements the Extended VMSAv7 MMU. The MMU supports:

ARMv7-A Virtual Memory System Architecture (VMSA).
Security Extensions.
Large Physical Address Extensions (LPAE).
Virtualization Extensions.

The Extended VMSAv7 MMU controls address translation, access permissions, and memory attributes determination and checking, for memory accesses.

See the ARM Architecture Reference Manual for a full architectural description of the Extended VMSAv7.

The MMU controls table walk hardware that accesses translation tables in memory. The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. The MMU enables fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in the L1 and L2 Translation Look-aside Buffers (TLBs).

The Cortex-A15 MMU features include the following:

32-entry fully-associative L1 instruction TLB.
Two separate 32-entry fully associative L1 TLBs for data load and store pipelines.
4-way set-associative 512-entry L2 TLB in each processor.
Intermediate table walk caches.
The TLB entries contain a global indicator or an Address Space Identifier (ASID) to permit context switches without TLB flushes.
The TLB entries contain a Virtual Machine Identifier (VMID) to permit virtual machine switches without TLB flushes.

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