All the processors share an integrated L2 cache and GIC. Each processor has the same configuration for NEON, VFP, and L1 ECC or parity.

If you configure the design for one processor, it retains the system level coherency support and the ACP slave port.

If you configure the design to exclude VFP, NEON is not available. You cannot configure the design to exclude VFP but include NEON.

If you configure the design to exclude the GIC, SPIs and the remaining GIC signals are not available, except PERIPHBASE[39:15].

The L2 tag RAM register slice option adds register slices to the L2 tag RAMs. The L2 data RAM register slice option adds register slices to the L2 data RAMs. Table 1.2 lists valid combinations of the L2 tag RAM and L2 data RAM register slice options.

If L2 arbitration register slice is included, an additional pipeline stage for the CPU-L2 arbitration logic interface is added to the L2 arbitration logic.

If L2 logic idle clock gating is present, most of the L2 logic is dynamically clock gated with a different clock than the GIC and Generic Timer. If L2 logic idle clock gating is not present, the L2 logic is not dynamically clock gated, and shares the same clock as the GIC and Generic Timer. The clock gate generator for the L2 logic is also removed. Having dynamic clock gating of the L2 logic can provide lower power dissipation, but at the cost of a more complex clock tree implementation.

If regional clock gating is present, an additional level of clock gating occurs for several logic blocks such as the register banks. Having regional clock gating can potentially provide lower power dissipation, but at the cost of a more complex clock tree implementation.