1.5. Configurable options

Table 1.1 lists the configurable options for the Cortex-A15 MPCore processor.

Table 1.1. Cortex-A15 MPCore processor configurable options

FeatureRange of options
Number of processors

Up to four processors

L2 cache size

L2 cache size of:

  • 512KB.

  • 1MB.

  • 2MB.

  • 4MB.

L2 tag RAM register slice

0 or 1

L2 data RAM register slice

0, 1 or 2

L2 arbitration register slice

Included or Not

L2 logic idle gated clock

Included or Not

Regional gated clocks[a]

Included or Not

ECC/parity support

Supported in L1 and L2, L2 only, or none

NEON

Included or Not

VFP

Included or Not

Generic Interrupt Controller

Included or Not

Shared Peripheral Interrupts

0 to 224, in steps of 32

Processor clock stop pins[a]

Included or Not

Power switch and clamp pinsIncluded or Not

[a] This feature is not available in revisions prior to r3p0.


Note

  • All the processors share an integrated L2 cache and GIC. Each processor has the same configuration for NEON, VFP, and L1 ECC or parity.

  • If you configure the design for one processor, it retains the system level coherency support and the ACP slave port.

  • If you configure the design to exclude VFP, NEON is not available. You cannot configure the design to exclude VFP but include NEON.

  • If you configure the design to exclude the GIC, SPIs and the remaining GIC signals are not available, except PERIPHBASE[39:15].

  • The L2 tag RAM register slice option adds register slices to the L2 tag RAMs. The L2 data RAM register slice option adds register slices to the L2 data RAMs. Table 1.2 lists valid combinations of the L2 tag RAM and L2 data RAM register slice options.

  • If L2 arbitration register slice is included, an additional pipeline stage for the CPU-L2 arbitration logic interface is added to the L2 arbitration logic.

  • If L2 logic idle clock gating is present, most of the L2 logic is dynamically clock gated with a different clock than the GIC and Generic Timer. If L2 logic idle clock gating is not present, the L2 logic is not dynamically clock gated, and shares the same clock as the GIC and Generic Timer. The clock gate generator for the L2 logic is also removed. Having dynamic clock gating of the L2 logic can provide lower power dissipation, but at the cost of a more complex clock tree implementation.

  • If regional clock gating is present, an additional level of clock gating occurs for several logic blocks such as the register banks. Having regional clock gating can potentially provide lower power dissipation, but at the cost of a more complex clock tree implementation.

Table 1.2 shows valid combinations of the L2 tag RAM and L2 data RAM register slice options.

Table 1.2. Valid combinations of L2 tag and data RAM register slice

L2 tag RAM register sliceL2 data RAM register slice
00
01
02
11
12

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