7.6. Asynchronous errors

The L2 memory system has two outputs that indicate asynchronous error conditions. An asynchronous external error condition exists when either:

If an asynchronous error condition is detected, the corresponding bit in the L2 Extended Control Register is asserted. The asynchronous error condition can be cleared by writing 1'b0 to the corresponding bit of the L2ECTLR. Software can only clear the L2ECTLR. Any attempt to assert the error by writing the L2ECTLR is ignored. See L2 Extended Control Register for more information.

External errors on the ACE write response channel or on the ACE read data channel, associated with a write-allocate memory transaction, cause the nAXIERRIRQ signal to be asserted LOW.

Double-bit ECC errors or invalid accesses to the internal GIC interrupt controller cause the nINTERRIRQ signal to be asserted LOW.

Any external error associated with a load instruction of type ReadNoSnoop, ReadShared, ReadClean or ReadUnique is reported back to the requestor along with an error response and this might trigger an abort.External errors associated with cache maintenance operations of type CleanShared or CleanInvalid are silently dropped..

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