4.2.3. c2 registers

Table 4.4 shows the 32-bit wide CP15 system control registers when CRn is c2.

Table 4.4. c2 register summary

Op1CRmOp2NameResetDescription
0c00TTBR0UNK

Translation Table Base Register 0 and Register 1

  1TTBR1UNK

Translation Table Base Register 0 and Register 1

  2TTBCR

0x00000000[a]

Translation Table Base Control Register

4c02HTCRUNK

Hyp Translation Control Register

 c12VTCRUNK

Virtualization Translation Control Register, see the ARM Architecture Reference Manual

[a] The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-Secure copy of the register is 0x0. You must program the Non-Secure copy of the register with the required initial value, as part of the processor boot sequence.


Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412