12.6. Register summary

This section summarizes the PTM registers. For full descriptions of the PTM registers, see:

Note

  • Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.

  • In Table 12.4, access type is described as follows:

    RW

    Read and write.

    RO

    Read only.

    WO

    Write only.

All PTM registers are 32 bits wide. The PTM registers are defined in the CoreSight Program Flow Trace Architecture Specification. Table 12.4 lists all of the registers that are implemented in the PTM with their offsets from a base address. This base address is defined by the system integrator when placing the PTM in the Debug APB memory map.

Table 12.4. PTM register summary

Base offset

Function

Type

Description

PTM configuration
 

0x000

Main Control

RWMain Control Register
 

0x004

Configuration Code

ROConfiguration Code Register
 0x008Trigger EventRWCoreSight Program Flow Trace Architecture Specification
 

0x010

StatusRWCoreSight Program Flow Trace Architecture Specification
 

0x014

System ConfigurationRO

System Configuration Register

TraceEnable control

 0x018

TraceEnable Start/Stop Control

RW

TraceEnable Start/Stop Control Register
 

0x020

TraceEnable Event

RW

CoreSight Program Flow Trace Architecture Specification
 

0x024

TraceEnable Control

RW

TraceEnable Control Register 1

Address comparators

 

0x040-0x05C

Address Comparator Value 1- 8

RW

CoreSight Program Flow Trace Architecture Specification
 

0x080-0x09C

Address Comparator Access Type 1- 8

RW

Counters

 

0x140-0x144

Counter Reload Value 1-2

RW

CoreSight Program Flow Trace Architecture Specification
 

0x150-0x154

Counter Enable 1-2

RW

 

0x160-0x164

Counter Reload Event 1-2

RW

 

0x170-0x174

Counter Value 1-2

RW

Sequencer registers

 

0x180-0x194

Sequencer State Transition Event 1-6

RW

CoreSight Program Flow Trace Architecture Specification
 

0x19C

Current Sequencer State

RW

CoreSight Program Flow Trace Architecture Specification
External output event
 

0x1A0-0x1A4

External Output Event 1-2

RW

CoreSight Program Flow Trace Architecture Specification

Context ID comparators

 

0x1B0

Context ID Comparator Value 1

RW

CoreSight Program Flow Trace Architecture Specification
 

0x1BC

Context ID Comparator Mask

RW

CoreSight Program Flow Trace Architecture Specification
General control
 

0x1E0

Synchronization Frequency

RW

Synchronization Frequency Register
 

0x1E4

ID

RO

See ETM ID Register
 

0x1E8

Configuration Code ExtensionRO

Configuration Code Extension Register

 0x1ECExtended External Input SelectionRWExtended External Input Selection Register
 0x1F8Timestamp EventRWCoreSight Program Flow Trace Architecture Specification
 

0x1FC

Auxiliary Control RegisterRW Auxiliary Control Register
 0x200CoreSight Trace IDRWCoreSight Program Flow Trace Architecture Specification
 0x204VMID Comparator valueRWCoreSight Program Flow Trace Architecture Specification
 0x300OS Lock Access SpecificationWOCoreSight Program Flow Trace Architecture Specification
 0x304OS Lock StatusROCoreSight Program Flow Trace Architecture Specification
 0x310Power Down ControlRWPower Down Control Register
 0x314Power Down StatusROCoreSight Program Flow Trace Architecture Specification
Integration registers
 0xEDCMiscellaneous OutputsWOMiscellaneous Output Register
 0xEE0Miscellaneous InputsROMiscellaneous Input Register
 0xEE8TriggerWOTrigger Register
 0xEECATB Data 0WOFigure 12.15
 0xEF0ATB Control 2ROATB Control Register 2
 0xEF4ATB IdentificationWOATB Identification Register
 0xEF8ATB Control 0WOATB Control Register 0
 

0xF00

Integration Mode ControlRWIntegration Mode Control Register
 

0xFA0

Claim Tag SetRWCoreSight Program Flow Trace Architecture Specification
 

0xFA4

Claim Tag ClearRWCoreSight Program Flow Trace Architecture Specification
 

0xFB0

Lock AccessWOCoreSight Program Flow Trace Architecture Specification
 

0xFB4

Lock StatusROCoreSight Program Flow Trace Architecture Specification
 0xFB8Authentication StatusROCoreSight Program Flow Trace Architecture Specification
 0xFC8Device ConfigurationROCoreSight Program Flow Trace Architecture Specification
 0xFCCDevice TypeROCoreSight Program Flow Trace Architecture Specification
Peripheral and Component ID registers
 0xFD0Peripheral ID4ROPeripheral Identification Registers
 0xFD4Peripheral ID5RO
 0xFD8Peripheral ID6RO
 0xFDCPeripheral ID7RO
 0xFE0Peripheral ID0RO
 0xFE4Peripheral ID1RO
 0xFE8Peripheral ID2RO
 0xFECPeripheral ID3RO
 0xFF0Component ID0ROComponent Identification Registers
 0xFF4Component ID1RO
 0xFF8Component ID2RO
 0xFFCComponent ID3RO

For more information about these registers and the packets implemented by the PTM, see the CoreSight Program Flow Trace Architecture Specification.

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