4.2.7. c7 registers

Table 4.8 shows the 32-bit wide CP15 system control registers when CRn is c7.

Table 4.8. c7 register summary

Op1CRmOp2NameResetDescription
0c04NOPUNK

No Operation, see the ARM Architecture Reference Manual

 c10ICIALLUISUNK

Invalidate all instruction caches to PoU Inner Shareable, see the ARM Architecture Reference Manual

  6BPIALLISUNK

Invalidate all branch predictors Inner Shareable, see the ARM Architecture Reference Manual

 c40PAR

UNK

Physical Address Register

 c50ICIALLUUNK

Invalidate all instruction caches to PoU, see the ARM Architecture Reference Manual

  1ICIMVAUUNK

Invalidate instruction caches by MVA to PoU, see the ARM Architecture Reference Manual

  4CP15ISBUNK

Instruction Synchronization Barrier operation, see the ARM Architecture Reference Manual

  6BPIALLUNK

Invalidate all branch predictors, see the ARM Architecture Reference Manual

  7BPIMVAUNK

Invalidate MVA from branch predictors, see the ARM Architecture Reference Manual

 c61DCIMVACUNK

Invalidate data cache line by MVA to PoC, see the ARM Architecture Reference Manual

  2DCISWUNK

Invalidate data cache line by set/way, see the ARM Architecture Reference Manual

 c80ATS1CPRUNK

Stage 1 current state PL1 read, see the ARM Architecture Reference Manual

  1ATS1CPWUNK

Stage 1 current state PL1 write, see the ARM Architecture Reference Manual

  2ATS1CURUNK

Stage 1 current state unprivileged read, see the ARM Architecture Reference Manual

  3ATS1CUWUNK

Stage 1 current state unprivileged write, see the ARM Architecture Reference Manual

  4ATS12NSOPRUNK

Stages 1 and 2 Non-secure PL1 read, see the ARM Architecture Reference Manual

  5ATS12NSOPWUNK

Stages 1 and 2 Non-secure PL1 write, see the ARM Architecture Reference Manual

  6ATS12NSOURUNK

Stages 1 and 2 Non-secure unprivileged read, see the ARM Architecture Reference Manual

  7ATS12NSOUWUNK

Stages 1 and 2 Non-secure unprivileged write, see the ARM Architecture Reference Manual

 c101DCCMVACUNK

Clean data cache line by MVA to PoC, see the ARM Architecture Reference Manual

  2DCCSWUNK

Clean data cache line by set/way, see the ARM Architecture Reference Manual

  4CP15DSBUNK

Data Synchronization Barrier operation, see the ARM Architecture Reference Manual

  5CP15DMBUNK

Data Memory Barrier operation, see the ARM Architecture Reference Manual

 c111DCCMVAUUNK

Clean data cache line by MVA to PoU, see the ARM Architecture Reference Manual

 c131NOPUNK

No Operation, see the ARM Architecture Reference Manual

 c141DCCIMVACUNK

Clean and invalidate data cache line by MVA to PoC, see the ARM Architecture Reference Manual

  2DCCISWUNK

Clean and invalidate data cache line by set/way, see the ARM Architecture Reference Manual

4c80ATS1HRUNK

Stage 1 Hyp mode read, see the ARM Architecture Reference Manual

  1ATS1HWUNK

Stage 1 Hyp mode write, see the ARM Architecture Reference Manual


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