7.1. About the L2 memory system

The L2 memory system consists of a tightly-coupled L2 cache and an integrated Snoop Control Unit (SCU), connecting up to four processors within a Cortex-A15 MPCore device. The L2 memory system also interfaces with an AMBA 4 (ACE) interconnect and an Accelerator Coherency Port (ACP) that is implemented as an AXI3 slave interface.

The features of the L2 memory system include:

Note

The Cortex-A15 MPCore processor does not support TLB or cache lockdown.

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