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Home > Program Trace Macrocell > Register descriptions > Peripheral Identification Registers |
The Peripheral Identification Registers provide standard information required for all CoreSight components. They are a set of eight registers, listed in register number order in Table 12.22.
Table 12.22. Summary of the Peripheral ID Registers
Register | Value | Offset |
---|---|---|
Peripheral ID4 | 0x04 | 0xFD0 |
Peripheral ID5 | 0x00 | 0xFD4 |
Peripheral ID6 | 0x00 | 0xFD8 |
Peripheral ID7 | 0x00 | 0xFDC |
Peripheral ID0 | 0x5F | 0xFE0 |
Peripheral ID1 | 0xB9 | 0xFE4 |
Peripheral ID2 | 0x3B | 0xFE8 |
Peripheral ID3 | 0x00 | 0xFEC |
Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.
The CoreSight Program Trace Flow Architecture Specification describes these registers.