Cortex-A15 MPCore Technical Reference ManualRevision: r3p2
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3.3.2. Register description

This section describes the Cortex-A15 Jazelle Extension registers. Table 3.1 provides cross references to individual registers.

Jazelle Identity Register

The JIDR characteristics are:

Purpose

Enables software to determine the implementation of the Jazelle Extension provided by the processor.

Usage constraints

The JIDR is:

  • A read-only register.

  • Accessible from all privilege levels.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1.

Figure 3.1 shows the JIDR bit assignments.

Figure 3.1. JIDR bit assignments

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Table 3.2 shows the JIDR bit assignments.

Table 3.2. JIDR bit assignments

BitsNameFunction
[31:0]-

Reserved, RAZ


To access the JIDR, read the CP14 register with:

MRC p14, 7, <Rd>, c0, c0, 0; Read Jazelle Identity Register

Jazelle OS Control Register

The JOSCR characteristics are:

Purpose

Provides operating system control of the use of the Jazelle Extension.

Usage constraints

The JOSCR is:

  • A read/write register.

  • Accessible only from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1.

The JOSCR is a 32-bit register with bits[31:0] reserved, RAZ/WI.

To access the JOSCR, read or write the CP14 register with:

MRC p14, 7, <Rd>, c1, c0, 0;  Read Jazelle OS Control Register

MCR p14, 7, <Rd>, c1, c0, 0;  Write Jazelle OS Control Register

Jazelle Main Configuration Register

The JMCR characteristics are:

Purpose

Provides control of the Jazelle Extension features.

Usage constraints

The JMCR is:

  • A read/write register, with access rights that depend on the current privilege level:

    • Write-only in unprivileged level.

    • Read-write at PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1.

The JMCR is a 32-bit register with bits[31:0] reserved, RAZ/WI.

To access the JMCR, read or write the CP14 register with:

MRC p14, 7, <Rd>, c2, c0, 0;  Read Jazelle Main Configuration Register

MCR p14, 7, <Rd>, c2, c0, 0;  Write Jazelle Main Configuration Register
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