4.2.9. c9 registers

Table 4.10 shows the 32-bit wide CP15 system control registers when CRn is c9.

Table 4.10. c9 register summary

Op1CRmOp2NameResetDescription
0c120PMCR0x410F3000

Performance Monitor Control Register

  1PMNCNTENSETUNK

Performance Monitor Count Enable Set Register, see the ARM Architecture Reference Manual

  2PMNCNTENCLRUNK

Performance Monitor Count Enable Clear Register, see the ARM Architecture Reference Manual

  3PMOVSRUNK

Performance Monitor Overflow Flag Status Register, see the ARM Architecture Reference Manual

  4PMSWINCUNK

Performance Monitor Software Increment Register, see the ARM Architecture Reference Manual

  5PMSELRUNK

Performance Monitor Event Counter Selection Register, see the ARM Architecture Reference Manual

  6PMCEID00x3FFF0F3F

Performance Monitor Common Event Identification Register 0

  7PMCEID10x00000000Performance Monitor Common Event Identification Register 1
 c130PMCCNTRUNK

Performance Monitor Cycle Count Register, see the ARM Architecture Reference Manual

  1PMXEVTYPERUNK

Performance Monitor Event Type Select Register, see the ARM Architecture Reference Manual

  2PMXEVCNTRUNK

Performance Monitor Event Count Register, see the ARM Architecture Reference Manual

 c140PMUSERENR0x00000000

Performance Monitor User Enable Register, see the ARM Architecture Reference Manual

  1PMINTENSETUNK

Performance Monitor Interrupt Enable Set Register, see the ARM Architecture Reference Manual

  2PMINTENCLRUNK

Performance Monitor Interrupt Enable Clear Register, see the ARM Architecture Reference Manual

  3PMOVSSETUNK

Performance Monitor Overflow Flag Status Set Register, see the ARM Architecture Reference Manual

1c02L2CTLR0x00000000[a]

L2 Control Register

  3L2ECTLR0x00000000

L2 Extended Control Register

[a] The reset value depends on the processor configuration.


Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412