12.7.1. Main Control Register

The ETMCR characteristics are:

Purpose

Controls general operation of the PTM, such as whether tracing is enabled or is cycle-accurate.

Usage constraints

There are no usage constraints.

Configurations

Available in all PTM configurations.

Attributes

See the register summary in Table 12.4.

Figure 12.2 shows the ETMCR bit assignments.

Figure 12.2. ETMCR bit assignments

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Table 12.5 shows the ETMCR bit assignments.

Table 12.5. ETMCR bit assignments

BitsNameFunction
[31]-

SBZP.

[30]VMID trace enable

This bit controls VMID tracing. Set this bit to 1 to enable VMID tracing. The reset value is 0.

[29]Return stack enable

Set this bit to 1 to enable use of the return stack. The reset value is 0.

[28]Timestamp enable

Set this bit to 1 to enable timestamping. The reset value is 0.

[27:25]Processor select

RAZ. This bit is not implemented.

[24]Instrumentation resources access control

RAZ. This bit is not implemented.

[23:16]-

SBZP.

[15:14]ContextIDsize

The possible value of this field are:

b00

No Context ID tracing.

b01

One byte traced, Context ID bits[7:0].

b10

Two bytes traced, Context ID bits[15:0].

b11

Four bytes traced, Context ID bits[31:0].

The reset value is 0.

Note

The PTM traces only the number of bytes specified, even if the new Context ID value is larger than this.

[13]-

SBZP.

[12]CycleAccurate

Set this bit to 1 to enable cycle-accurate tracing. The reset value is 0.

[11]-

SBZP.

[10]ProgBit

Programming bit. You must set this bit to 1 to program the PTM, and clear it to 0 when programming is complete. The reset value is 1.

[9]Debug request control

When this bit is set to 1 and the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables a debugger to force the processor into Debug state. The reset value is 0.

[8]BranchBroadcast

Set this bit to 1 to enable branch broadcasting. Branch broadcasting traces the addresses of direct branch instructions. You must not set this bit to 1 if bit[29] of this register is set to 1 to enable use of the return stack. Behavior is unpredictable if you enable both use of the return stack and branch broadcasting. The reset value is 0.

[7]Stall processor

RAZ. This bit is not implemented.

[6:1]-SBZP.
[0]Powerdown

A pin controlled by this bit enables the PTM power to be controlled externally. The external pin is PTMPWRDOWN, or inverted as PTMPWRUP.

This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, the PTM must be powered down and disabled, and then operated in a low power mode with all clocks stopped.

When this bit is set to 1, writes to some registers and fields might be ignored. You can always write to the following registers and fields:

  • ETMCR, bit[0] and bits[27:25].

  • ETMLAR.

  • ETMCLAIMSET.

  • ETMCLAIMCLR.

  • ETMOSLAR.

When ETMCR is written with this bit set to 1, writes to bits other than bits[27:25, 0] might be ignored. The reset value is 1.


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