4.2.10. c10 registers

Table 4.11 shows the 32-bit wide CP15 system control registers when CRn is c10.

Table 4.11. c10 register summary

Op1CRmOp2NameResetDescription
0c20PRRR0x00098AA4

Primary Region Remap Register, see the ARM Architecture Reference Manual

  0MAIR0[a]0x00098AA4Memory Attribute Indirection Register 0
  1NMRR0x44E048E0

Normal Memory Remap Register, see the ARM Architecture Reference Manual

  1MAIR1[b]0x44E048E0

Memory Attribute Indirection Register 1

 c30AMAIR0UNK

Auxiliary Memory Attribute Indirection Register 0

  1AMAIR1UNK

Auxiliary Memory Attribute Indirection Register 1

4c20HMAIR0UNK

Hyp Memory Attribute Indirection Register 0, see the ARM Architecture Reference Manual

  1HMAIR1UNK

Hyp Memory Attribute Indirection Register 1, see the ARM Architecture Reference Manual

 c30HAMAIR0UNKHyp Auxiliary Memory Attribute Indirection Register 0
  1HAMAIR1UNK

Hyp Auxiliary Memory Attribute Indirection Register 1

[a] The processor behavior for all implementation defined encodings in the MAIR0 register is unpredictable.

[b] The processor behavior for all implementation defined encodings in the MAIR1 register is unpredictable.


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