Cortex-A15 MPCore Technical Reference ManualRevision: r3p2
Home > System Control > Register summary > c12 registers

4.2.11. c12 registers

Table 4.12 shows the 32-bit wide CP15 system control registers when CRn is c12.

Table 4.12. c12 register summary

Op1CRmOp2NameResetDescription
0c00VBAR

0x00000000[a]

Vector Base Address Register, see the ARM Architecture Reference Manual

  1MVBARUNK

Monitor Vector Base Address Register, see the ARM Architecture Reference Manual

 c10ISRUNK

Interrupt Status Register, see the ARM Architecture Reference Manual

4c00HVBARUNK

Hyp Vector Base Address Register, see the ARM Architecture Reference Manual

[a] The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.


Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412
PDF file icon  PDF version
Home > System Control > Register summary > c12 registers