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Home > Program Trace Macrocell > Register descriptions > ETM ID Register |
The ETMIDR characteristics are:
Holds the PTM architecture variant.
Defines the programmers model for the PTM.
There are no usage constraints.
Available in all PTM configurations.
See the register summary in Table 12.4.
Figure 12.7 shows the ETMIDR bit assignments.
Table 12.10 shows the ETMIDR bit assignments.
Table 12.10. ID Register bit assignments
Bits | Name | Function |
---|---|---|
[31:24] | Implementer code | Indicates the implementer:
|
[23:21] | - | RAZ. |
[20] | - | RAO. |
[19] | Security Extensions supported | Support for Security Extensions. The value of this bit is 1, indicating that the processor implements the ARM architecture Security Extensions. |
[18] | 32-bit Thumb instructions supported | Support for 32-bit Thumb instructions. The value of this bit is 1, indicating that a 32-bit Thumb instruction is traced as a single instruction. |
[17:16] | - | RAZ. |
[15:12] | - | This field reads as b1111. |
[11:8] | Major architecture version | Indicates the major architecture version number. This field reads as b0011. |
[7:4] | Minor architecture version | Indicates the minor architecture version number. This field reads as b0001. |
[3:0] | Implementation revision | Indicates the implementation revision. This field reads as b0011. |