4.3.62. Auxiliary Control Register 2

Note

This register is not available in revisions prior to r3p0.

The ACTLR2 characteristics are:

Purpose

Provides configuration and control options for the processor.

Usage constraints

The ACTLR2:

  • Is a read/write register.

  • Is Common to the Secure and Non-secure states.

  • Is only accessible from PL1 or higher, with access rights that depend on the mode:

    • Read/write in Secure PL1 modes.

    • Read-only and write-ignored in Non-secure PL1 and PL2 modes.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.14.

Figure 4.61 shows the ACTLR2 bit assignments.

Figure 4.61. ACTLR2 bit assignments

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Table 4.76 shows the ACTLR2 bit assignments.

Table 4.76. Auxiliary Control Register 2 bit assignments

BitsNameFunction
[31]Enable CPU regional clock gates

Enable CPU regional clock gates:

0

Disables the CPU regional clock gates. When this bit is cleared, the regional clock gate enable is tied HIGH. This is the reset value.

1

Enables the CPU regional clock gates for additional clock gating. When this bit is set, the regional clock gates can gate-off the clock and potentially reduce dynamic power dissipation.

[30:1]-

Reserved.

[0]Execute data cache clean as data cache clean/invalidate

Execute data cache clean as data cache clean and invalidate:

0

Normal behavior, executes data cache clean as data cache clean. This is the reset value.

1

Executes data cache clean as data cache clean and invalidate.


To access the ACTLR2, read or write the CP15 register with:

MRC p15, 1, <Rt>, c15, c0, 4; Read Auxiliary Control Register 2
MCR p15, 1, <Rt>, c15, c0, 4; Write Auxiliary Control Register 2
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