4.2.24. Performance monitor registers

Table 4.24 shows the 32-bit wide performance monitor registers.

Table 4.24. Performance monitor registers

NameCRnOp1CRmOp2ResetDescription
PMCRc90c1200x410F3000

Performance Monitor Control Register

PMNCNTENSET   1UNK

Performance Monitor Count Enable Set Register, see the ARM Architecture Reference Manual

PMNCNTENCLR   2UNK

Performance Monitor Count Enable Clear Register, see the ARM Architecture Reference Manual

PMOVSR   3UNK

Performance Monitor Overflow Flag Status Register, see the ARM Architecture Reference Manual

PMSWINC   4UNK

Performance Monitor Software Increment Register, see the ARM Architecture Reference Manual

PMSELR   5UNK

Performance Monitor Event Counter Selection Register, see the ARM Architecture Reference Manual

PMCEID0   60x3FFF0F3F

Performance Monitor Common Event Identification Register 0

PMCEID1   70x00000000Performance Monitor Common Event Identification Register 1
PMCCNTR  c130UNK

Performance Monitor Cycle Count Register, see the ARM Architecture Reference Manual

PMXEVTYPER   1UNK

Performance Monitor Event Type Select Register, see the ARM Architecture Reference Manual

PMXEVCNTR   2UNK

Performance Monitor Event Count Register, see the ARM Architecture Reference Manual

PMUSERENR  c1400x00000000

Performance Monitor User Enable Register, see the ARM Architecture Reference Manual

PMINTENSET   1UNK

Performance Monitor Interrupt Enable Set Register, see the ARM Architecture Reference Manual

PMINTENCLR   2UNK

Performance Monitor Interrupt Enable Clear Register, see the ARM Architecture Reference Manual

PMOVSSET   3UNK

Performance Monitor Overflow Flag Status Set Register, see the ARM Architecture Reference Manual


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