4.2.17. Virtual memory control registers

Table 4.17 shows the Virtual memory control registers.

Table 4.17. Virtual memory registers

NameCRnOp1CRmOp2ResetWidthDescription
SCTLRc10c000x00C50078[a]32-bit

System Control Register

TTBR0c20c00UNK32-bit

Translation Table Base Register 0 and Register 1

-0c2-64-bit

Translation Table Base Register 0 and Register 1

TTBR1c20c01UNK32-bit

Translation Table Base Register 0 and Register 1

-1c2-64-bit

Translation Table Base Register 0 and Register 1

TTBCRc20c02

0x00000000[b]

32-bit

Translation Table Base Control Register

DACRc30c00UNK32-bit

Domain Access Control Register, see the ARM Architecture Reference Manual

PRRRc100c200x00098AA432-bit

Primary Region Remap Register, see the ARM Architecture Reference Manual

MAIR0   0UNK32-bit

Memory Attribute Indirection Register 0, see the ARM Architecture Reference Manual

NMRR   10x44E048E032-bit

Normal Memory Remap Register, see the ARM Architecture Reference Manual

MAIR1   1UNK32-bit

Memory Attribute Indirection Register 1, see the ARM Architecture Reference Manual

AMAIR0   c30UNK32-bit

Auxiliary Memory Attribute Indirection Register 0

AMAIR1   1UNK32-bit

Auxiliary Memory Attribute Indirection Register 1

CONTEXTIDRc130c01UNK32-bit

Process ID Register, see the ARM Architecture Reference Manual

[a] The reset value depends on primary inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4.17 assumes these signals are set to zero.

[b] The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-Secure copy of the register is 0x0. You must program the Non-Secure copy of the register with the required initial value, as part of the processor boot sequence.


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