4.3.46. Hyp Syndrome Register

The HSR characteristics are:


Holds syndrome information for an exception taken in Hyp mode.

Usage constraints

The HSR is:

  • A read/write register.

  • Only accessible from Hyp mode or from Monitor mode when SCR.NS is 1

  • unknown when executing in Non-secure modes other than Hyp mode.


Available in all configurations.


See the register summary in Table 4.26.

Figure 4.37 shows the HSR bit assignments.

Figure 4.37. HSR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 4.68 shows the HSR bit assignments.

Table 4.68. HSR bit assignments


Exception class. The exception class for the exception that is taken in Hyp mode.

When zero, this field indicates that the reason for the exception is not known. In this case, the other fields in this register are unknown. Otherwise, the field holds the exception class for the exception. See the ARM Architecture Reference Manual for more information.


Instruction length. Indicates the size of the instruction that has been trapped to Hyp mode:


16-bit instruction.


32-bit instruction.

This field is not valid for:

  • Instruction Aborts.

  • Data Aborts that do not have ISS information, or for which the ISS is not valid.

In these cases the field is UNK/SBZP.


Instruction specific syndrome. The interpretation of this field depends on the value of the EC field. See Encoding of ISS[24:20] when HSR[31:30] is 0b00.

Encoding of ISS[24:20] when HSR[31:30] is 0b00

For EC values that are nonzero and have the two most-significant bits 0b00, ISS[24:20] provides the condition field for the trapped instruction, together with a valid flag for this field. The encoding of this part of the ISS field is:

CV, ISS[24]

Condition valid. Possible values of this bit are:


The COND field is not valid.


The COND field is valid.

When an instruction is trapped, CV is set to 1.

COND, ISS[23:20]

The Condition field for the trapped instruction. This field is valid only when CV is set to 1.

If CV is set to 0, this field is UNK/SBZP.

When an instruction is trapped, the COND field is 0xE.

Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G