Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A

ChangeLocationAffects
First release--

Table B.2. Differences between issue A and issue B

ChangeLocationAffects

Added L2 arbitration register slice as another Cortex-A15 configurable option

Table 1.1

r0p0

Added a note to indicate that if L2 arbitration register slice is included, an additional pipeline stage is added to the L2 arbitration logic

Configurable options

r0p0
Updated the table for valid combinations of L2 tag and data RAM register slice

Table 1.2

r0p0

Added a new section for event communication using WFE and SEV instructions

Event communication using WFE and SEV instructions

r0p0

Updated the reset value of the Main ID Register

r1p0

Updated bits[23:20] of the Main ID RegisterMain ID Registerr1p0

Added bit[10] Disable non-secure debug array read to the L2 Auxiliary Control Register

L2 Auxiliary Control Register

r0p0
Updated description of Non-cacheable streaming enhancementNon-cacheable streaming enhancementr0p0
Updated ID number of Software Generated Interrupt (SGI)Interrupt sourcesr0p0
Added event number 0x62 and 0x63 to the PMU event tableTable 11.7r1p0

Updated description for bits[3:0] of the ETMIDR

ETM ID Register

r1p0

Updated the value for Peripheral ID2 Register

r1p0
Updated trigger input name of PMU generated interruptTable 13.1r0p0
Clarified the step instructions for using the Advanced SIMD and VFP in Secure stateUsing the Advanced SIMD and VFP in Secure state onlyr0p0
Clarified the step instructions for using the Advanced SIMD and VFP in Secure state and Non-secure stateUsing the Advanced SIMD and VFP in Secure state and Non-secure state other than Hyp moder0p0
Clarified the step instructions for using the Advanced SIMD and VFP in Hyp modeUsing the Advanced SIMD and VFP in Hyp moder0p0
Clarified description of the GIC signalsTable A.4r0p0

Clarified description of the EVENTI and EVENTO signals

Table A.6

r0p0
Updated and moved SYNCREQx from Miscellaneous PTM interface signals table to ATB interface signals tableTable A.28r0p0

Table B.3. Differences between issue B and issue C

ChangeLocationAffects
Updated description for L2 wait for interrupt L2 Wait for Interruptr2p0

Updated the reset value of the Main ID Register

r2p0
Corrected the reset value of the ID_PFR0 RegisterAll revisions
Updated bits[23:20] of the Main ID RegisterMain ID Registerr2p0
Clarified description of bits[11:8] of the ID_PFR0 RegisterProcessor Feature Register 0All revisions
Updated L2ACTLR bit[5] of the L2 Auxiliary Control RegisterL2 Auxiliary Control Registerr2p0
Updated description of GIC memory-mapGIC memory-mapr2p0

Updated the value for Peripheral ID2 Register

r2p0
Renamed PMCCFILTR to PMXEVTYPER31 in the PMU register summary tableTable 11.1r2p0

Updated description for bits[3:0] of the ETMIDR

ETM ID Registerr2p0
Updated the GIC configuration section GIC configurationr2p0
Updated description of the nVIRQ and nVFIQ input pinsTable A.4r2p0

Table B.4. Differences between issue C and issue D

ChangeLocationAffects

Updated the reset value of the Main ID Register

r2p1
Added the reset values for MAIR0 and MAIR1Table 4.11r2p1
Updated bits[23:20] of the Main ID RegisterMain ID Registerr2p1
Clarified description for bits[11:10] and bit[12] of the L2 Control RegisterL2 Control Registerr2p1
Added a new section for cache maintenance transactions in the Level 2 Memory System chapterCache maintenance transactionsr2p1
Clarified that some memories within the L2 memory system support ECC when configuredError Correction Coder2p1
Added a section in the L2 memory system for asynchronous errorsAsynchronous errorsr2p1
Updated the DBGDIDR bit assignmentsTable 10.2r2p1
Updated the field name for bits[63:40] of the Debug Self Address Offset RegisterTable 10.16r2p1
Clarified description for debug registersChapter 10 Debugr2p1
Updated ARUSERS[5:0] for the read address channelTable A.23r2p1

Table B.5. Differences between issue D and issue E

ChangeLocationAffects

Added regional clock gates and processor clock stop pins as additional configuration options

r3p0

Added description for CPUCLKOFF inputs

Clocks

r3p0

Added description for regional clock gating

Regional clock gating

r3p0
Updated the L2 Wait For Interrupt timing diagram to show that CLKEN is asserted before the Internal L2 clock signal

Figure 2.13

All revisions

Added new section for processor retention in WFI and WFE mode

Processor retention in WFI and WFE mode

r3p0

Updated the sequence for powering down the processor and the NEON and VFP power domains

Processor power domain

r3p0

Added the multiprocessor powerdown mode as one of the power sequences that ARM recommends

Multiprocessor powerdown mode

r3p0

Adding the deassertion of ACINACTM or AINACTS as conditions for exiting L2 WFI mode

L2 Wait for Interrupt

All revisions

Updated the reset value of the Main ID Register

r3p0
Updated bits[23:20] of the Main ID RegisterMain ID Registerr3p0
Added Auxiliary Control Register 2r3p0
Modified the L2 Auxiliary Control RegisterL2 Auxiliary Control Registerr3p0
Removed the footnote and updated the value for Peripheral ID2 RegisterAll revisions
Updated the Performance Monitor Common Event Register 0 bit assignment table to indicate which event is implementedTable 11.4All revisions
Corrected the reset value for bit[10] of the ETMCR Table 12.5All revisions
Updated bit[0] of the ETMCRTable 12.5All revisions
Updated bits[3:0] of the ETMIDRTable 12.10All revisions
Updated the clock and clock enable signals tableTable A.1r3p0
Updated the write address channel signals tableTable A.10r3p0
Updated the power management signals tableTable A.7r3p0

Table B.6. Differences between issue E and issue F

ChangeLocationAffects

Updated the reset value of the Main ID Register

r3p1
Updated bits[23:20] of the Main ID RegisterMain ID Registerr3p1
Updated information about external errors associated with a load instruction and with cache maintenance operations.Asynchronous errorsAll revisions

Table B.7. Differences between issue F and issue G

ChangeLocationAffects
Clarified description for CLKENClocksr3p2
Updated the reset sequence for a full soft reset on the processorSoft resetr3p2
Updated information on L2 Wait for Interrupt L2 Wait for Interruptr3p2

Updated the reset value of the Main ID Register

r3p2
Updated bits[23:20] of the Main ID RegisterMain ID Registerr3p2
Corrected description for bits[26:25] of the Auxiliary Control RegisterAuxiliary Control RegisterAll revisions
Clarified information about intermediate table walk cachesIntermediate table walk cachesAll revisions
Updated description for instruction cache speculative memory accessesInstruction cache speculative memory accessesr3p2
Clarified information about external memory errorsAsynchronous errorsAll revisions
Added Debug Device ID Register 1Debug Device ID Register 1r3p2
Added event mnemonic column to the PMU events tableTable 11.7All revisions

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