2.3.2. Resets

The processor has the following reset inputs:

nCPUPORESET[3:0]

The nCPUPORESET signal initializes all the processor logic, including the NEON and VFP logic, Debug, PTM, breakpoint and watchpoint logic in the processor CLK domain. Each processor has one nCPUPORESET reset input.

nCORERESET[3:0]

The nCORERESET signal initializes the processor logic, including the NEON and VFP logic but excludes the Debug, PTM, breakpoint and watchpoint logic. Each processor has one nCORERESET reset input.

nCXRESET[3:0]

The nCXRESET signal initializes the NEON and VFP logic. This reset can be used to hold the NEON and VFP unit in a reset state so that the power to the unit can be safely applied during power up. Each processor has one nCXRESET reset input.

nDBGRESET[3:0]

The nDBGRESET signal initializes the Debug, PTM, breakpoint and watchpoint logic in the processor CLK domain. Each processor has one nDBGRESET reset input.

nPRESETDBG

The nPRESETDBG signal initializes the shared Debug APB, CTI, and CTM logic in the PCLKDBG domain.

nL2RESET

The nL2RESET signal initializes the shared L2 memory system, Interrupt Controller, and Timer logic.

All resets are active-LOW inputs. The reset signals lets you reset different parts of the processor independently. Table 2.1 shows the areas of the processor controlled by the various reset signals. In this table, [3:0] specifies the processor configuration.

Table 2.1. Areas controlled by reset signals

Reset signalProcessor[a] (CLK)NEON and VFP (CLK)Debug and PTM [b] (CLK)Debug APB, CTI, and CTM (PCLKDBG)L2 memory system, GIC, and Generic Timer (CLK)
nCPUPORESET[3:0]ResetResetReset- -
nCORERESET[3:0]ResetReset- - -
nCXRESET[3:0]- Reset- - -
nDBGRESET[3:0]- - Reset- -
nPRESETDBG- - - Reset -
nL2RESET- - - -Reset

[a] Processor logic, excluding NEON and VFP, Debug, PTM, breakpoint and watchpoint logic.

[b] Debug, PTM, breakpoint and watchpoint logic.


Table 2.2 shows the valid combinations for the reset signals to enable:

In Table 2.2, [3:0] specifies the processor configuration and [n] designates the processor that is reset.

Table 2.2. Valid reset combinations

Reset combinationSignalsValueDescription
Full powerup reset for entire Cortex-A15 MPCore processor

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

all = 0

all = 0[a]

all = 0[a]

all = 0[a]

0

0

All logic is held in reset.
Individual processor powerup reset with Debug (PCLKDBG) reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

[n] = 0

[n] = 0[a]

[n] = 0[a]

[n] = 0[a]

0

1

Individual processor and Debug (PCLKDBG) are held in reset, so that the processor and Debug (PCLKDBG) can be powered up.
All processor and L2 reset with Debug (PCLKDBG) active

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

all = 0

all = 0[a]

all = 0[a]

all = 0[a]

1

0

All processors and L2 are held in reset, so they can be powered up. This enables external debug over power down for all processors.
Individual processor powerup reset with Debug (PCLKDBG) active

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

[n] = 0

[n] = 0[a]

[n] = 0[a]

[n] = 0[a]

1

1

Individual processor is held in reset, so that the processor can be powered up. This enables external debug over power down for the processor that is held in reset.
All processors software reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

all = 1

all = 0

all = 0[b]

all = 1

1

1

All logic excluding Debug and PTM (CLK and PCLKDBG) and L2 are held in reset. All breakpoints and watchpoints are retained.
All processors software reset and L2 reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

all = 1

all = 0

all = 0[b]

all = 1

1

0

All logic excluding Debug and PTM (CLK and PCLKDBG) is held in reset. All breakpoints and watchpoints are retained.
Individual processor software reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

[n] = 1

[n] = 0

[n] = 0[b]

[n] = 1

1

1

Individual processor logic excluding Debug and PTM (CLK) is held in reset. Breakpoints and watchpoints for that processor are retained.
NEON and VFP reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

[n] = 1

[n] = 1

[n] = 0

[n] = 1

1

1

NEON and VFP unit is held in reset, so that the unit can be powered up.
All processors Debug (CLK) and Debug (PCLKDBG) reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

all = 1

all = 1

all = 1

all = 0

0

1

Debug and PTM (CLK and PCLKDBG) are held in reset.
Individual processor Debug (CLK) reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

[n] = 1

[n] = 1

[n] = 1

[n] = 0

1

1

Individual processor Debug and PTM (CLK) is held in reset.
Debug (PCLKDBG) reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

all = 1

all = 1

all = 1

all = 1

0

1

Debug (PCLKDBG) is held in reset, so that Debug (PCLKDBG) can be powered up.
NEON and VFP and Debug (PCLKDBG) reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

[n] = 1

[n] = 1

[n] = 0

[n] = 1

0

1

NEON and VFP and Debug (PCLKDBG) are held in reset, so that NEON and VFP and Debug (PCLKDBG) can be powered up.
NEON and VFP and Debug (CLK) reset

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

[n] = 1

[n] = 1

[n] = 0

[n] = 0

1

1

NEON and VFP and Debug (CLK) are held in reset.
Run mode

nCPUPORESET [3:0]

nCORERESET [3:0]

nCXRESET [3:0]

nDBGRESET [3:0]

nPRESETDBG

nL2RESET

1

1

1

1

1

1

No logic is held in reset.

[a] For powerup reset or processor reset, nCPUPORESET must be asserted. The remaining processor resets, nCORERESET, nCXRESET, and nDBGRESET can be asserted, but is not required.

[b] For soft reset, nCORERESET must be asserted, nCXRESET can be asserted, but is not required.


Note

  • nL2RESET resets the shared L2 memory system logic, GIC and Generic Timer that is common to all processors. This reset must not be asserted while any individual processor is active.

  • nPRESETDBG resets the shared Debug in PCLKDBG domain that is common to all processors. This reset must not be asserted while any individual processor is actively being debugged in normal operating mode or during external debug over power down.

  • If your implementation does not include the NEON and VFP unit, you can tie the nCXRESET input HIGH.

There are specific requirements that you must meet to reset each reset domain listed in Table 2.1. Not adhering to these requirements can lead to a reset domain that is not functional.

The reset sequences in the following sections are the only reset sequences that ARM recommends. Any deviation from these sequences might cause an improper reset of that reset domain.

The supported reset sequences are:

Powerup reset

The full powerup reset initializes all logic in the Cortex-A15 MPCore processor. You must apply powerup reset to the Cortex-A15 MPCore processor when power is first applied to the SoC. Logic in all clock domains are placed in a benign state following the deassertion of the reset sequence.

Figure 2.7 shows the full powerup reset sequence for the Cortex-A15 MPCore processor.

Figure 2.7. Powerup reset timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


On full powerup reset for the Cortex-A15 MPCore processor, perform the following reset sequence:

  1. Apply nCPUPORESET, nL2RESET, and nPRESETDBG. The remaining processor resets, nCORERESET, nCXRESET, and nDBGRESET can be asserted, but is not required.

  2. nCPUPORESET and nL2RESET must be asserted for at least 16 CLK cycles. nPRESETDBG must be asserted for at least16 PCLKDBG cycles. Holding the resets for this duration ensures that the resets have propagated to all locations within the processor.

  3. nL2RESET must be deasserted in the same cycle as the processor resets, or before any of the processor resets are deasserted.

Individual processor powerup reset initializes all logic in a single processor. You must apply the powerup reset when the individual processor is in powered state. In implementations where each processor has its own power supply, the powerup reset holds the processor in a reset state so that power to the processor can be safely applied. You must apply the correct sequence before applying a powerup reset to that processor.

For individual processor powerup reset:

  • nCPUPORESET for that processor must be asserted for at least 16 CLK cycles.

  • nL2RESET must not be asserted while any individual processor is active.

  • nPRESETDBG must not be asserted while any individual processor is actively being debugged in normal operating mode or during external debug over power down.

Soft reset

The full soft reset initializes all logic in each of the individual processor apart from the Debug and PTM logic in the CLK domain. All breakpoints and watchpoints are retained during a soft reset sequence. By asserting only nCORERESET, the reset domains controlled by nDBGRESET, nPRESETDBG, and nL2RESET, that is, the Debug and PTM in CLK, Debug APB in PCLKDBG, and the shared L2 memory system, GIC, and Generic Timer domains, are not reset.

Figure 2.8 shows the full soft reset sequence for the Cortex-A15 MPCore processor.

Figure 2.8. Soft reset timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


On full soft reset for the Cortex-A15 MPCore processor, perform the following reset sequence:

  1. You must apply steps 1 to 8 in the processor powerdown sequence, see Processor power domain, and wait until STANDBYWFI is asserted, indicating that the processor is idle, before asserting nCORERESET for that processor.

    Note

    For a single processor configuration you can omit step 3 that clears the ACTLR SMP bit.

  2. Apply nCORERESET, nCXRESET can be asserted, but is not required.

  3. After both resets have been asserted for 5 cycles, the clamps can be released.

  4. nCORERESET must be asserted for at least 16 CLK cycles.

  5. If nCXRESET is asserted, both resets must be deasserted in the same cycle.

Individual processor soft reset initializes all logic in a single processor apart from its Debug, PTM, breakpoint and watchpoint logic. Breakpoints and watchpoints for that processor are retained. You must apply the correct sequence before applying soft reset to that processor.

For individual processor soft reset:

  • You must apply steps 1 to 8 in the processor powerdown sequence, see Processor power domain, and wait until STANDBYWFI is asserted, indicating that the processor is idle, before asserting nCORERESET for that processor.

    Note

    For a single processor configuration you can omit step 3 that clears the ACTLR SMP bit.

  • nCORERESET for that processor must be asserted for at least 16 CLK cycles.

  • nL2RESET must not be asserted while any individual processor is active.

  • nPRESETDBG must not be asserted while any individual processor is actively being debugged in normal operating mode.

NEON and VFP reset

An additional reset controls the NEON and VFP unit, independently of the processor reset. You can use this reset to hold the NEON and VFP unit in a reset state so that the power to this unit can be safely applied during power up.

The reset cycle timing requirements for nCXRESET are identical to those for nCORERESET. nCXRESET must be held for a minimum of 16 CLK cycles when asserted to guarantee that the NEON and VFP unit has entered a reset state.

Figure 2.9 shows the NEON and VFP reset sequence.

Figure 2.9. NEON and VFP reset timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Note

If your implementation does not include the NEON and VFP unit, you can tie the nCXRESET inputs HIGH.

Debug CLK reset

Use nDBGRESET to reset the processor, Debug, PTM, breakpoint and watchpoint logic in the CLK domain.

To safely reset the Debug CLK unit, nDBGRESET must be asserted for a minimum of 16 CLK cycles.

Figure 2.10 shows the Debug CLK reset sequence.

Figure 2.10. Debug CLK reset timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Debug PCLKDBG reset

Use nPRESETDBG to reset the Debug APB, CTI and CTM logic in the PCLKDBG domain. This reset holds the Debug PCLKDBG unit in a reset state so that the power to the unit can be safely applied during power up.

To safely reset the Debug PCLKDBG unit, nPRESETDBG must be asserted for a minimum of 16 PCLKDBG cycles.

Figure 2.11 shows the Debug PCLKDBG reset sequence.

Figure 2.11. Debug PCLKDBG reset timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Memory arrays reset

During a processor reset, the following memory arrays in the processor are invalidated at reset:

  • Branch Prediction arrays such as BTB, GHB, and Indirect Predictor.

  • L1 instruction and data TLBs.

  • L1 instruction and data caches.

  • L2 unified TLB.

In addition to these processor memory arrays, during a powerup reset, the following shareable memory arrays are invalidated at reset:

  • L2 duplicate snoop tag RAM.

  • L2 prefetch stride queue RAM.

  • L2 unified cache RAM, if L2RSTDISABLE is tied LOW.

The L1 instruction and data cache resets can take up to 128 CLK cycles after the deasserting edge of the reset signals, with each array being reset in parallel. Depending on the size of the L2 cache, the L2 cache reset can take 640 CLK cycles for a 512KB L2 cache and 5120 CLK cycles for a 4MB L2 cache. The L2 cache reset occurs in the background, in parallel with the L1 cache resets. The processor can begin execution in non-cacheable state, but any attempt to perform cacheable transactions stalls the processor until the appropriate cache reset is complete.

The branch prediction arrays require 512 CLK cycles to reset after the deasserting edge of reset. The processor begins execution with branch prediction disabled, any attempt to enable branch prediction with the SCTLR.Z bit, stalls the processor until the branch prediction cache resets are complete.

The Cortex-A15 MPCore processor has an input signal, L2RSTDISABLE, that controls the L2 cache hardware reset process. The usage models for the L2RSTDISABLE signal are as follows:

  • When the Cortex-A15 MPCore processor powers up for the first time, L2RSTDISABLE must be held LOW to invalidate the L2 cache using the L2 cache hardware reset mechanism.

  • For systems that do not retain the L2 cache RAM contents while the L2 memory system is powered down, L2RSTDISABLE must be held LOW to invalidate the L2 cache using the L2 cache hardware reset mechanism.

  • For systems that retain the L2 cache RAM contents while the L2 memory system is powered down, L2RSTDISABLE must be held HIGH to disable the L2 cache hardware reset mechanism.

The L2RSTDISABLE signal is sampled during nL2RESET assertion and must be held a minimum of 32 CLK cycles after the deasserting edge of nL2RESET.

Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412