2.4.3. Power modes

You can control the power domains independently to give different combinations of powerup and powerdown domains. However, only some powerup and powerdown domain combinations are valid and supported.

Table 2.3 shows the valid powerup and powerdown domain combinations for the different possible modes of operation.

Table 2.3. Valid power modes

ModeProcessor[a] (CLK)NEON and VFP (CLK)Debug-APB, CTI, and CTM (PCLKDBG)L2 RAMs[b] (CLK)L2 control, IC, Timer (CLK)
Full Run modePowered upPowered upPowered upPowered upPowered up
Run mode with Debug powered downPowered upPowered upPowered downPowered upPowered up
Run mode with NEON and VFP powered downPowered upPowered downPowered upPowered upPowered up
Run mode with NEON, VFP and Debug powered downPowered upPowered downPowered downPowered upPowered up
L2 and Debug powered upPowered downPowered downPowered upPowered upPowered up
L2 RAMs retain with Debug powered upPowered downPowered downPowered upRetention statePowered down
Debug powered upPowered downPowered downPowered upPowered downPowered down
L2 powered upPowered downPowered downPowered downPowered upPowered up
L2 RAMs retain or dormant modePowered downPowered downPowered downRetention statePowered down
ShutdownPowered downPowered downPowered downPowered downPowered down

[a] Processor logic, including Debug, PTM, breakpoint and watchpoint logic, but excluding NEON and VFP.

[b] L2 cache tag bank RAMs that include tag, dirty, data, and data ECC RAMs if ECC support is present.


There are specific requirements that you must meet to power up and power down each power domain within the processor. Not adhering to these requirements can lead to unpredictable results.

The powerup and powerdown sequences in the following sections are the only power sequences that ARM recommends. Any deviation from these sequences can lead to unpredictable results.

The supported powerup and powerdown sequences are:

Note

The powerup and powerdown sequences require that you isolate the powerup domain before power is removed from the powerdown domain. You must clamp the outputs of the powerdown domain to benign values to prevent data corruption or Unpredictable behavior in the powerup domain. The SoC controls the clamping using the nISOLATExx input pins.

Processor power domain

If a processor is not required, you can reduce leakage power by turning off the power to the processor logic. The processor logic refers to all processor logic, including Debug, PTM, breakpoint and watchpoint logic, but excluding the NEON and VFP unit. Powering down the processor requires that you also power down the NEON and VFP unit.

To enable the processor to be powered down, the implementation must place the processor and NEON and VFP unit on separately controlled power supplies. In addition, you must clamp the outputs of the processor and the NEON and VFP unit to benign values while the entire processor is powered down, to indicate that the processor is idle.

To power down the processor and the NEON and VFP power domains, apply the following sequence:

  1. Clear the SCTLR.C bit, or HSCTLR.C bit if in Hyp mode, to prevent additional data cache allocation.

  2. Clean and invalidate all data from the L1 data cache. The L2 duplicate snoop tag RAM for this processor is now empty. This prevents any new data cache snoops or data cache maintenance operations from other processors in the MPCore device being issued to this processor.

  3. Switch the processor from Symmetric Multiprocessing (SMP) mode to Asymmetric Multiprocessing (AMP) mode by clearing the ACTLR SMP bit. Clearing the SMP bit enables the processor to be taken out of coherency by preventing the processor from receiving cache, TLB, or BTB maintenance operations broadcast by other processors in the MPCore device.

  4. Ensure that the system does not send interrupts to the processor that is being powered down.

  5. Execute an ISB instruction to ensure that all of the CP15 register changes from the previous steps have been committed.

  6. Execute a DSB instruction to ensure that all cache, TLB and branch predictor maintenance operations issued by any processor in the MPCore device before the SMP bit was cleared have completed.

  7. Execute a WFI instruction and wait until the STANDBYWFI output is asserted to indicate that the processor is in idle and low power state.

  8. Activate the processor and the NEON and VFP output clamps by asserting the nISOLATECPU and nISOLATECX inputs LOW.

  9. Remove power from the processor and the NEON and VFP power domains.

Note

For a single processor configuration you can omit step 3 that clears the ACTLR SMP bit.

To power up the processor and the NEON and VFP power domains, apply the following sequence:

  1. Assert nCPUPORESET.

  2. Apply power to the processor and the NEON and VFP power domains while keeping nCPUPORESET asserted.

  3. Release the processor and the NEON and VFP output clamps by deasserting nISOLATECPU and nISOLATECX.

  4. Continue a normal powerup reset sequence.

To power up the processor while keeping the NEON and VFP unit powered down, apply the following sequence:

  1. Assert nCPUPORESET.

  2. Apply power to the processor power domain while keeping nCPUPORESET asserted. Be sure to keep the NEON and VFP domain powered down.

  3. Release the processor output clamps by deasserting nISOLATECPU. Be sure to keep nISOLATECX asserted.

  4. Continue a normal powerup reset sequence while nISOLATECX remain asserted.

NEON and VFP power domain

If the NEON and VFP unit is not required, you can reduce leakage power by turning off the power to the unit. While the unit is powered down, any Advanced SIMD or VFP instructions executed take the Undefined Instruction exception.

To enable the NEON and VFP unit to be powered down, the implementation must place the unit on a separately controlled power supply. In addition, you must clamp the outputs of the NEON and VFP unit to benign values while the unit is powered down, to indicate that the unit is idle.

To power down the NEON and VFP power domain while the processor is in reset, apply the following sequence:

  1. Assert nCPUPORESET for powerup reset or nCORERESET for soft reset.

  2. Activate the NEON and VFP unit output clamps by asserting the nISOLATECX input LOW.

  3. Remove power from the NEON and VFP power domain. If the processor is executing a powerup reset sequence or is first powering up, keep the NEON and VFP power domain off while applying power to the other power domains.

  4. Complete and exit the reset sequence.

Note

If the NEON and VFP output clamps are released without following one of the specified NEON and VFP powerup sequences, the results are Unpredictable.

To power down the NEON and VFP power domain while the processor is not in reset, apply the following sequence:

  1. You must disable access to the NEON and VFP unit by setting the CPACR and HCPTR. See Coprocessor Access Control Register and Hyp Coprocessor Trap Register. All outstanding Advanced SIMD and VFP instructions retire and all subsequent Advanced SIMD and VFP instructions cause an Undefined Instruction exception.

    MRC P15, 0, <Rd>, c1, c0, 2;    Read CPACR
    
    BIC <Rd>, <Rd>, #0x00F00000;    Clear CP10 and CP11 bits
    
    MCR p15, 0, <Rd>, c1, c0, 2;    Write CPACR
    
    MRC p15, 4, <Rd>, c1, c1, 2;    Read HCPTR
    
    ORR <Rd>, <Rd>, #0x00000C00;    Set TCP10 and TCP11 bits        
    
    MCR p15, 4, <Rd>, c1, c1, 2;    Write HCPTR
    
  2. Execute an ISB instruction to ensure that all of the CP15 register changes in step 1 have been committed.

  3. Software must signal to the external SoC that the NEON and VFP unit is disabled.

  4. Activate the NEON and VFP output clamps by asserting the nISOLATECX input LOW.

  5. Remove power from the NEON and VFP power domain.

Note

If the NEON and VFP output clamps are released without following one of the specified NEON and VFP powerup sequences, the results are Unpredictable.

To power up the NEON and VFP power domain while the processor is in reset, apply the following sequence:

  1. Assert nCPUPORESET for powerup reset or nCORERESET for soft reset.

  2. Apply power to the NEON and VFP power domain while keeping nCPUPORESET or nCORERESET asserted.

  3. Release the NEON and VFP output clamps by deasserting nISOLATECX.

  4. Complete and exit the reset sequence.

  5. Software must poll the external SoC to determine that it is safe to enable the NEON and VFP unit.

After the completion of the reset sequence, you can enable the NEON and VFP unit by setting CPACR and HCPTR appropriately. See Coprocessor Access Control Register and Hyp Coprocessor Trap Register.

To power up the NEON and VFP power domain while the processor is not in reset, apply the following sequence:

  1. You must disable access to the NEON and VFP unit by setting the CPACR and HCPTR. This is a safety precaution in case software enabled access to the NEON and VFP unit while the unit was powered down.

    MRC p15, 0, <Rd>, c1, c0, 2;  	 Read CPACR
    
    BIC <Rd>, <Rd>, #0x00F00000;	   Clear cp10 and cp11 bits
    
    MCR p15, 0, <Rd>, c1, c0, 2;   Write CPACR
    
    MRC p15, 4, <Rd>, c1, c1, 2;   	Read HCPTR
    
    ORR <Rd>, <Rd>, #0x00000C00;	   Set TCP10 and TCP11 bits
    
    MCR p15, 4, <Rd>, c1, c1, 2;	   Write HCPTR
    
  2. Execute an ISB instruction to ensure that all of the CP15 register changes in step 1 have been committed.

  3. Software must signal to the external SoC that it is safe to power up the NEON and VFP unit.

  4. Assert nCXRESET.

  5. Apply power to the NEON and VFP power domain while keeping nCXRESET asserted.

  6. Deassert nCXRESET. The NEON and VFP unit requires a minimum of 16 CLK cycles to complete its reset sequence. The SoC must wait until the unit has completed its reset sequence before releasing the NEON and VFP clamps.

  7. Release the NEON and VFP output clamps by deasserting nISOLATECX.

  8. Software must poll the external SoC to determine that it is safe to enable the NEON and VFP unit.

After the completion of the reset sequence, you can enable the NEON and VFP unit by setting the CPACR and HCPTR appropriately.

Debug power domain

If the Cortex-A15 MPCore processor is running in an environment where debug facilities are not required for any of the processors in the MPCore device, you can reduce leakage power by turning off the power to the debug unit in the PCLKDBG domain.

To enable the debug unit to be powered down, the implementation must place the unit on a separately controlled power supply. In addition, you must clamp the outputs of the debug unit to benign values while the unit is powered down, to indicate that the unit is idle.

To power down the Debug APB PCLKDBG power domain, apply the following sequence:

  1. Activate the debug output clamps by asserting the nISOLATEPDBG input LOW.

  2. Remove power from the debug PCLKDBG domain.

Note

If the debug output clamps are released without following the specified debug powerup sequence, the results are Unpredictable.

To power up the Debug APB PCLKDBG power domain, apply the following sequence:

  1. Assert nPRESETDBG.

  2. Apply power to the debug PCLKDBG power domain while keeping nPRESETDBG asserted.

  3. Release the debug output clamps by deasserting nISOLATEPDBG.

  4. If the SoC uses the debug hardware, deassert nPRESETDBG.

External debug over power down

The Cortex-A15 MPCore processor provides support for external debug over power down. If any or all of the processors are powered down, the SoC can still use the debug facilities if the debug PCLKDBG domain is powered up.

To enable external debug over power down, the implementation must place the processor and the debug PCLKDBG unit on separately controlled power supplies. If the processor is powered down while the debug PCLKDBG unit is powered up, you must clamp all outputs from the processor power domain to the debug power domain to benign values, to indicate that the processor is idle.

To power down the processor and the NEON and VFP power domains for external debug over powerdown support, apply the following additional step to the processor and NEON and VFP powerdown sequence, as described in Processor power domain, after STANDBYWFI is asserted in step 7:

  • Assert DBGPWRDWNREQ to indicate that the processor debug resources are not available for APB accesses. Wait for DBGPWRDWNACK to be asserted.

When power is removed from the processor and NEON and VFP power domains, keep the debug PCLKDBG unit powered up.

To power up the processor power domain after external debug over powerdown support is no longer required, apply the following additional step to the processor and NEON and VFP powerup sequence, as described in Processor power domain, after releasing the processor and NEON VFP output clamps in step 3:

  • Deassert DBGPWRDWNREQ to indicate that processor debug resources are available. There is no requirement for the SoC to wait for the deassertion of DBGPWRDWNACK.

Dormant mode

The Cortex-A15 MPCore processor supports Dormant mode, where all the processors, Debug PCLKDBG, and L2 control logic are powered down while the L2 cache RAMs are powered up and retain state. The RAM blocks that remain powered up during Dormant mode are:

  • L2 tag RAMs.

  • L2 dirty RAMs.

  • L2 data RAMs.

  • L2 data ECC RAMs, if ECC support is present.

To support Dormant mode, the L2 cache RAMs must be implemented in separate power domains. In addition, you must clamp all inputs to the L2 cache RAMs to benign values, to avoid corrupting data when the processors and L2 control power domains enter and exit power down state.

Before entering Dormant mode, the architectural state of the Cortex-A15 MPCore processor, excluding the contents of the L2 cache RAMs that remain powered up, must be saved to external memory.

To exit from Dormant mode to Run mode, the SoC must perform a full powerup reset sequence. The SoC must assert the reset signals until power is restored. After power is restored, the Cortex-A15 MPCore processor exits the powerup reset sequence, and the architectural state must be restored.

To enter Dormant mode, apply the following sequence:

  1. Clear the SCTLR C bit to prevent additional data cache allocation.

  2. Clean and invalidate all data from the L1 data cache. The L2 duplicate snoop tag RAM for this processor is now empty. This prevents any new data cache snoops or data cache maintenance operations from other processors in the MPCore device being issued to this processor.

  3. Switch the processor from SMP mode to AMP mode by clearing the ACTLR SMP bit. Clearing the SMP bit enables the processor to be taken out of coherency by preventing the processor from receiving cache, TLB, or BTB maintenance operations broadcast by other processors in the MPCore device.

  4. Save architectural state, if required. These state saving operations must ensure that the following occur:

    • All ARM registers, including the CPSR and SPSR, are saved.

    • All system registers are saved.

    • All debug related state is saved.

  5. Execute an ISB instruction to ensure that all of the CP15 register changes from the previous steps have been committed.

  6. Execute a DSB instruction to ensure that all cache, TLB and branch predictor maintenance operations issued by any processor in the MPCore device before the SMP bit was cleared have completed. In addition, this ensures that all state saving has completed.

  7. Execute a WFI instruction and wait until the STANDBYWFI output is asserted, to indicate that the processor is in idle and low power state.

  8. Repeat the previous steps for all processors, and wait for all STANDBYWFI outputs to be asserted.

  9. The SoC asserts the input pin ACINACTM to idle the AXI master interface after all responses are received and before it sends any new transactions on the interface. The SoC asserts the input pin AINACTS to idle the ACP slave interface after all responses are received and before it sends any new transactions on the interface. When the L2 has completed the outstanding transactions for the AXI master and slave interfaces, STANDBYWFIL2 is asserted to indicate that L2 memory system is idle.

  10. When all processors STANDBYWFI and STANDBYWFIL2 are asserted, the Cortex-A15 MPCore processor is ready to enter Dormant mode.

  11. Activate the L2 cache RAM input clamps by asserting the nISOLATEL2MISC inputs LOW.

  12. Remove power from the processors, NEON and VFP unit, Debug, and L2 control power domains.

Note

For a single processor configuration you can omit step 3 that clears the ACTLR SMP bit.

To exit Dormant mode, apply the following sequence:

  1. Apply a normal powerup reset sequence. You must apply resets to the processors, NEON and VFP unit, Debug, and the L2 memory system logic until power is restored. During this reset sequence, L2RSTDISABLE must be held HIGH to disable the L2 cache hardware reset mechanism.

  2. When power has been restored, release the L2 cache RAM input clamps.

  3. Continue a normal powerup reset sequence with L2RSTDISABLE held HIGH. The L2RSTDISABLE must be held HIGH for a minimum of 32 CLK cycles after the deasserting edge of nL2RESET.

  4. The architectural state must be restored, if required.

Multiprocessor powerdown mode

The Cortex-A15 MPCore processor supports multiprocessor powerdown mode where all the Cortex-A15 MPCore processor power domains are shut down and all state is lost.

To power down the Cortex-A15 MPCore processor, apply the following sequence:

  1. Ensure all non-lead processors are in shutdown mode, see Processor power domain.

  2. For the remaining and lead processor, follow steps 1 and 2 in Processor power domain.

  3. Assert ACINACTM to idle the AXI master interface after all responses are received.

  4. Ensure the ACP master does not send further requests to the individual processor. Assert AINACTS to idle the ACP slave interface after all responses are received.

  5. Ensure any system snooping to the Cortex-A15 MPCore processor is disabled.

  6. Disable L2 prefetches by writing 0x00000400 to the L2 Prefetch Control Register. See L2 Prefetch Control Register.

  7. Execute an ISB instruction to ensure the L2 Prefetch Control Register write is complete. See L2 Prefetch Control Register.

  8. Execute a DSB instruction to ensure completion of any prior prefetch requests.

  9. Clean and invalidate all data from the L2 data cache.

  10. Ensure system interrupts to the Cortex-A15 MPCore processor are disabled.

  11. Set the DBGOSDLR.DLK, Double lock control bit, that forces the debug interfaces to be quiescent.

  12. Follow steps 3 to 9 in Processor power domain.

  13. Wait until the STANDBYWFIL2 output is asserted to indicate that the L2 memory system is idle.

  14. Activate the output clamps of the Cortex-A15 MPCore processor in the SoC.

  15. Remove power from the L2 control and L2 RAM power domains.

To power up the Cortex-A15 MPCore processor, apply the following sequence:

  1. For each processor in the MPCore device, assert nCPUPORESET LOW.

  2. For the lead processor in the MPCore device, assert nPRESETDBG and nL2RESET LOW, and hold L2RSTDISABLE LOW.

  3. Apply power to the processor, L2 control, L2 RAM and debug power domains while keeping the signals described in steps 1 and 2 LOW.

  4. Release the output clamps of the Cortex-A15 MPCore processor in the SoC.

  5. Continue a normal powerup reset sequence.

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