2.3.1. Clocks

The processor has the following clock inputs:

CLK

This is the main clock of the Cortex-A15 MPCore processor. All processors, the shared L2 memory system logic, the GIC, and the Generic Timer are clocked with a distributed version of CLK.

PCLKDBG

This is the APB clock that controls the Debug APB, CTI and CTM logic in the PCLKDBG domain. PCLKDBG is asynchronous to CLK.

The processor has the following clock enable inputs:

ACLKENM

The AXI master interface is a synchronous AXI interface that can operate at any integer multiple that is equal to or slower than the main processor clock, CLK, using the ACLKENM signal. For example, you can set the CLK to ACLKM frequency ratio to 1:1, 2:1, or 3:1, where ACLKM is the AXI master clock. ACLKENM asserts one CLK cycle prior to the rising edge of ACLKM. Software can change the CLK to ACLKM frequency ratio dynamically using ACLKENM.

Figure 2.2 shows a timing example of ACLKENM that changes the CLK to ACLKM frequency ratio from 3:1 to 1:1.

Figure 2.2. ACLKENM with CLK:ACLKM ratio changing from 3:1 to 1:1

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Note

Figure 2.2 shows the timing relationship between the AXI master clock, ACLKM and ACLKENM, where ACLKENM asserts one CLK cycle before the rising edge of ACLKM. It is important that the relationship between ACLKM and ACLKENM is maintained.

ACLKENS

ACP is a synchronous AXI slave interface that can operate at any integer multiple that is equal to or slower than the main processor clock, CLK, using the ACLKENS signal. For example, the CLK to ACLKS frequency ratio can be 1:1, 2:1, or 3:1, where ACLKS is the AXI slave clock. ACLKENS asserts one CLK cycle before the rising edge of ACLKS. The CLK to ACLKS frequency ratio can be changed dynamically using ACLKENS.

Figure 2.3 shows a timing example of ACLKENS that changes the CLK to ACLKS frequency ratio from 3:1 to 1:1.

Figure 2.3. ACLKENS with CLK:ACLKS ratio changing from 3:1 to 1:1

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Note

Figure 2.3 shows the timing relationship between the ACP clock, ACLKS and ACLKENS, where ACLKENS asserts one CLK cycle before the rising edge of ACLKS. It is important that the relationship between ACLKS and ACLKENS is maintained.

PCLKENDBG

The Debug APB interface is an asynchronous interface that can operate at any integer multiple that is equal to or slower than the APB clock, PCLKDBG, using the PCLKENDBG signal. For example, the PCLKDBG to internal PCLKDBG frequency ratio can be 1:1, 2:1, or 3:1. PCLKENDBG asserts one PCLKDBG cycle before the rising edge of the internal PCLKDBG. The PCLKDBG to internal PCLKDBG frequency ratio can be changed dynamically using PCLKENDBG.

Figure 2.4 shows a timing example of PCLKENDBG that changes the PCLKDBG to internal PCLKDBG frequency ratio from 2:1 to 1:1.

Figure 2.4. PCLKENDBG with PCLKDBG:internal PCLKDBG ratio changing from 2:1 to 1:1

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ATCLKEN

The ATB interface is a synchronous interface that can operate at any integer multiple that is slower than the main processor clock, CLK, using the ATCLKEN signal. For example, the CLK to ATCLK frequency ratio can be 2:1, 3:1, or 4:1, where ATCLK is the ATB bus clock. ATCLKEN asserts three CLK cycles before the rising edge of ATCLK. Three CLK cycles are required to permit propagation delay from the ATCLKEN input to the processor. The CLK to ATCLK frequency ratio can be changed dynamically using ATCLKEN.

Figure 2.5 shows a timing example of ATCLKEN where the CLK to ATCLK frequency ratio is 2:1.

Figure 2.5. ATCLKEN with CLK:ATCLK ratio at 2:1

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PERIPHCLKEN

This is the synchronous clock enable signal for the GIC. The GIC can operate at any integer multiple that is slower than the main processor clock, CLK, using the PERIPHCLKEN signal. For example, the CLK to internal GIC clock frequency ratio can be 2:1 or 3:1. PERIPHCLKEN asserts one CLK cycle prior to the rising edge of the internal IC clock. The CLK to internal IC clock frequency ratio can be changed dynamically using PERIPHCLKEN.

Note

If you configure your design to exclude the GIC, this signal does not exist.

Figure 2.6 shows a timing example of PERIPHCLKEN where the CLK to internal GIC frequency ratio is 2:1.

Figure 2.6. PERIPHCLKEN with CLK:internal IC clock ratio at 2:1

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CLKEN

This is the main clock enable for all internal clocks in the Cortex-A15 MPCore processor that are derived from CLK. There is one CLK cycle delay between the assertion of CLKEN and the internal clocks that are enabled. When all the processors and L2 are in WFI mode, you can place the processor in a low power state using the CLKEN input. This disables all internal clocks, excluding the asynchronous Debug APB PCLKDBG domain. See L2 Wait for Interrupt.

CPUCLKOFF

Note

This configuration option is not available in revisions prior to r3p0.

These pins are only present if you configure the Cortex-A15 MPCore processor to include them. If you configure the processor to include the CPUCLKOFF pins, there is one CPUCLKOFF input pin and a new top-level clock gate instantiated for each processor. When CPUCLKOFF is asserted, the processor clock is stopped. This pin must be tied LOW or 1'b0 under normal functional operation, and can only be asserted under strict conditions. Having external control of the processor clock enable permits the SoC to assert CPUCLKOFF when the processor is already powered down, or when the processor is powered up. However, CPUCLKOFF must be deasserted after power has been completely restored, to permit the powerup reset sequence to complete.

Note

Because configuring the Cortex-A15 MPCore processor with the CPUCLKOFF pins adds a new top-level clock gate for each processor, it might increase the clock skew between the processors.

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