The processor implements an AMBA 4 AXI Coherency Extensions (ACE) master interface and an AMBA 3 AXI Accelerator Coherency Port (ACP) slave interface. Both the ACE and ACP support a hardware configurable 64-bit or 128-bit data width. See the AMBA AXI and ACE Protocol Specification for more information.

ACE is an extension to the AXI protocol and provides the following enhancements:

ACP is an implementation of an AMBA 3 AXI slave interface. It supports memory coherent accesses to the Cortex-A15 MPCore memory system, but cannot receive coherent requests, barriers or distributed virtual memory messages.