2.4.1. Dynamic power management

This section describes the following dynamic power management features in the Cortex-A15 MPCore processor:

Processor Wait for Interrupt

Wait for Interrupt is a feature of the ARMv7-A architecture that puts the processor in a low power state by disabling most of the clocks in the processor while keeping the processor powered up. This reduces the power drawn to the static leakage current, leaving a small clock power overhead to enable the processor to wake up from WFI mode.

A processor enters into WFI mode by executing the WFI instruction.

When executing the WFI instruction, the processor waits for all instructions in the processor to retire before entering the idle or low power state. The WFI instruction ensures that all explicit memory accesses occurred before the WFI instruction in program order, have retired. For example, the WFI instruction ensures that the following instructions received the required data or responses from the L2 memory system:

  • Lload instructions.

  • Cache and TLB maintenance operations.

  • Store exclusives instructions.

In addition, the WFI instruction ensures that store instructions have updated the cache or have been issued to the L2 memory system.

While the processor is in WFI mode, the clocks in the processor are temporarily enabled without causing the processor to exit WFI mode, when any of the following events are detected:

  • An L2 snoop request that must be serviced by the processor L1 data cache.

  • A cache, TLB or BTB maintenance operation that must be serviced by the processor L1 instruction cache, data cache, instruction TLB, data TLB, or BTB.

  • An APB access to the debug or trace registers residing in the processor power domain.

Exit from WFI mode occurs when the processor detects a reset or one of the WFI wake up events as described in the ARM Architecture Reference Manual.

On entry into WFI mode, STANDBYWFI for that processor is asserted. Assertion of STANDBYWFI guarantees that the processor is in idle and low power state. STANDBYWFI continues to assert even if the clocks in the processor are temporarily enabled because of an L2 snoop request, cache, TLB, and BTB maintenance operation or an APB access.

Figure 2.12 shows the upper bound for the STANDBYWFI deassertion timing after the assertion of nIRQ or nFIQ inputs.

Figure 2.12. STANDBYWFI deassertion timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Processor Wait for Event

Wait for Event is a feature of the ARMv7-A architecture that uses a locking mechanism based on events to put the processor in a low power state by disabling most of the clocks in the processor while keeping the processor powered up. This reduces the power drawn to the static leakage current, leaving a small clock power overhead to enable the processor to wake up from WFE mode.

A processor enters into WFE mode by executing the WFE instruction. When executing the WFE instruction, the processor waits for all instructions in the processor to complete before entering the idle or low power state. The WFE instruction ensures that all explicit memory accesses occurred before the WFE instruction in program order, have completed.

While the processor is in WFE mode, the clocks in the processor are temporarily enabled without causing the processor to exit WFE mode, when any of the following events are detected:

  • An L2 snoop request that must be serviced by the processor L1 data cache.

  • A cache, TLB or BTB maintenance operation that must be serviced by the processor L1 instruction cache, data cache, instruction TLB, data TLB, or BTB.

  • An APB access to the debug or trace registers residing in the processor power domain.

Exit from WFE mode occurs when the processor detects a reset, the assertion of the EVENTI input signal, or one of the WFI wake up events as described in the ARM Architecture Reference Manual.

On entry into WFE mode, STANDBYWFE for that processor is asserted. Assertion of STANDBYWFE guarantees that the processor is in idle and low power state. STANDBYWFE continues to assert even if the clocks in the processor are temporarily enabled because of an L2 snoop request, cache, TLB, and BTB maintenance operation or an APB access.

The upper bound for the STANDBYWFE deassertion timing after the assertion of nIRQ or nFIQ inputs is identical to STANDBYWFI as shown in Figure 2.12.

L2 Wait for Interrupt

When all the processors are in WFI mode, the shared L2 memory system logic that is common to all the processors can also enter a WFI mode. In L2 WFI mode, all internal clocks in the processor are disabled, with the exception of the asynchronous Debug PCLKDBG domain.

Entry into L2 WFI mode can only occur if specific requirements are met and the following sequence applied:

  • All processors are in WFI mode and therefore, all the processors STANDBYWFI outputs are asserted. Assertion of all the processors STANDBYWFI outputs guarantee that all the processors are in idle and low power state. All clocks in the processor, with the exception of a small amount of clock wake up logic, are disabled.

  • The SoC asserts the input pin ACINACTM after all responses are received and before it sends any new transactions on the AXI master interface. This prevents the L2 memory system from accepting any new requests from the AXI master interface and ensures that all outstanding transactions are complete.

  • The SoC asserts the input pin AINACTS after all responses are received and before it sends any new transactions on the ACP slave interface. This prevents the L2 memory system from accepting any new requests from the ACP slave interface and ensures that all outstanding transactions are complete.

  • When the L2 memory system completed the outstanding transactions for AXI interfaces, it can then enter the low power state, L2 WFI mode. On entry into L2 WFI mode, STANDBYWFIL2 is asserted. Assertion of STANDBYWFIL2 guarantees that the L2 is in idle and does not accept any new transactions.

  • The SoC can then deassert the CLKEN input to the Cortex-A15 MPCore processor to stop all remaining internal clocks within the Cortex-A15 MPCore processor that are derived from CLK. All clocks in the shared L2 memory system logic, Interrupt Controller and Timer, are disabled.

The SoC must assert the CLKEN input on a WFI wake up event to enable the L2 memory system and potentially the processor. There are two classes of wake up events:

  • An event that requires only the L2 memory system to be enabled.

  • An event that requires both the L2 memory and the processor to be enabled.

The following wake up events cause the L2 memory system and the processor to exit WFI mode:

  • A physical IRQ or FIQ interrupt.

  • A debug event.

  • Powerup or soft reset.

Wake up events that only require the L2 memory system to exit WFI mode include:

  • Deassertion of ACINACTM to service an external snoop request on the AC channel interface.

  • Deassertion of AINACTS to service an ACP transaction on the slave interface.

When the processor exits from WFI mode, STANDBYWFI for that processor is deasserted. When the L2 memory system logic exits from WFI mode, STANDBYWFIL2 is deasserted.

Figure 2.13 shows the L2 WFI timing for a 4-processor configuration.

Figure 2.13. L2 Wait For Interrupt timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Processor retention in WFI and WFE mode

Note

The processor retention in WFI and WFE mode is not available in revisions prior to r3p0.

When a processor is in WFI or WFE mode, the clocks to that processor are stopped. The clocks might start for short periods of time during the WFI or WFE mode to allow the processor to handle snoops or other short events without leaving WFI or WFE mode.

Whenever the clocks to a processor are stopped, it is possible for an external power controller to lower the voltage of that processor to a lower level where all state is retained while leakage is reduced. However, this is only possible if the external power controller can guarantee that the clocks do not restart without first allowing the voltage to be raised to the level required for normal operation. The Cortex-A15 MPCore processor has an interface that allows an external power controller to place one or more processors into a retention state. The external power controller ensures that the clocks do not restart without first allowing the power controller to exit the retention state.

When the clocks are stopped because the processor is in WFI or WFE mode, the QACTIVE signal is deasserted LOW for that processor as Figure 2.14 shows. This indicates that retention is possible for that processor. The external power controller can place that processor in retention state by asserting QREQn LOW. The Cortex-A15 MPCore processor accepts the retention request by asserting QACCEPTn LOW. While QREQn and QACCEPTn are both asserted LOW, the processor is in quiescent state and the clocks to that processor remain stopped as long as QREQn remains asserted LOW. The external power controller can safely lower the voltage of that processor to a retention level.

If the individual processor cannot safely enter quiescent state when QREQn is asserted LOW, the Cortex-A15 MPCore processor asserts QDENY HIGH instead of asserting QACCEPTn LOW. When this occurs, the external power controller cannot lower the voltage of that processor. The external power controller must then deassert QREQn HIGH, after which the processor deasserts QDENY LOW.

If the clocks for a quiescent processor must be restarted, for example, to handle a snoop or to exit the WFI or WFE mode, the QACTIVE signal asserts HIGH. This indicates to the external power controller that it must allow that processor to exit quiescent state. To do this, the external power controller must first restore that processor power domain to a stable running voltage. The external power controller then deasserts QREQn. When this signal is deasserted, the Cortex-A15 MPCore processor can restart the clocks to that individual processor and then deasserts QACCEPTn.

Figure 2.14 shows a typical sequence where the external power controller places the processor in retention state. The processor executes a WFI instruction. STANDBYWFI is asserted and QACTIVE is deasserted. The external power controller asserts QREQn LOW to indicate that it wants to put that processor into retention. While the processor is still in WFI mode and the clocks are stopped, QACCEPTn is asserted LOW. At this point, the processor is in quiescent state and the external power controller can lower the voltage. During retention, a snoop must access the cache of the quiescent processor. The QACTIVE signal is asserted HIGH to request an exit from retention. The external power controller raises the voltage of that processor to running levels and deasserts QREQn. The clocks are started and the snoop can proceed. QACCEPTn is then deasserted HIGH. After the snoop is complete, QACTIVE is deasserted LOW. QREQn and QACCEPTn are then asserted LOW. The processor has re-entered quiescent state and the external power controller can lower the voltage once again. When the processor is ready to exit WFI mode, QACTIVE is asserted HIGH. QREQn is then deasserted HIGH, the processor exits WFI mode, and QACCEPTn is deasserted HIGH.

Figure 2.14. WFI successful retention timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Figure 2.15 shows a sequence where the external power controller attempts to but fails to take a processor to retention voltage levels. The processor enters WFI mode and deasserts QACTIVE. The external power controller asserts QREQn LOW and QDENY is asserted HIGH, followed by the deassertions of QREQn and QDENY. This sequence is then repeated.

Note

Figure 2.15 shows that in the second denial sequence, QACTIVE is still deasserted when the retention request is denied. QACTIVE is an indication of processor activity, but is only a hint. A retention request can be accepted when QACTIVE is asserted HIGH, or denied when QACTIVE is deasserted.

Figure 2.15. WFI denied retention timing

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Each processor present has an independent set of pins QREQn, QACCEPTn, QDENY, and QACTIVE. QREQn is a fully asynchronous input and can only transition from deasserted HIGH to asserted LOW if QACCEPTn is deasserted HIGH and QDENY is deasserted LOW. After QREQn is asserted LOW, it must be held asserted LOW until either QACCEPTn is asserted LOW or QDENY is asserted HIGH. QREQn can then be deasserted HIGH, and must be held deasserted HIGH until both QACCEPTn is deasserted HIGH and QDENY is deasserted LOW.

The QACTIVE pin is an activity hint that is not part of the strict 4-phase handshake of the QREQn, QACCEPTn, and QDENY pins. If QACTIVE is asserted HIGH while a processor is in quiescent state, it indicates that the external power controller can, but is not required to, exit quiescent state. If QACTIVE is asserted HIGH while the processor is not in quiescent state, it indicates that the processor is not in WFI standby or WFE mode and there is not a likely processor retention opportunity. If QACTIVE is deasserted, it indicates that the processor is in WFI or WFE mode and there might be an opportunity to put the processor into quiescent state and lower its voltage.

Performance impact on the use of processer retention

The use of processor retention can impact performance. Any delay in deasserting QREQn when QACTIVE is asserted HIGH during quiescent state can delay the starting of the clocks to that processor. This directly impacts the performance of that processor if it exits WFI or WFE mode. This also impacts the performance of other processors or coherent memory masters if that processor is being restarted to handle a cache snoop. In general, only use this feature if the system can enter and exit the retention voltage level in a very short period of time.

Guidelines on the use of processor retention

As processors generally only stay in WFE mode for a short period of time, ARM recommends that you only take a processor into retention when it is in WFI mode.

If the L1 data cache of a processor that is in WFI mode contains data that is likely to be the target of frequent snoops from other processors, entering quiescent state and retention is likely to be inefficient.

When using the processor retention feature, you must consider the following points:

  • During processor reset, QREQn must be deasserted HIGH while QACCEPTn is asserted LOW.

  • Each QREQn request is followed by the assertion of either QACCEPTn or QDENY, but not both. QACCEPTn cannot be asserted LOW at the same time as QDENY is asserted HIGH.

  • QACTIVE, QACCEPTn and QDENY are synchronous outputs.

  • QREQn is an asynchronous input.

  • In a system that does not use the processor retention feature, QREQn must be tied HIGH.

  • QACTIVE is only a hint. The external power controller can assert QREQn LOW at any time after reset. If QACTIVE is asserted HIGH, it is likely that the retention request can be denied.

  • The Enable CPU WFI retention bit in the L2 Auxiliary Control Register, see L2 Auxiliary Control Register, must be set to enable this feature. If it is not set, all assertions of QREQn HIGH receive QDENY responses.

  • If any processor sets the Force NEON/VFP clock enable active or Force main clock enable active bits in the Auxiliary Control Register, see Auxiliary Control Register, this feature is disabled and all assertions of QREQn receive QDENY responses.

NEON and VFP clock gating

The Cortex-A15 MPCore processor supports dynamic high-level clock gating of the NEON and VFP unit to reduce dynamic power dissipation.

With the NEON and VFP unit powered up, the clock to the unit is enabled when an Advanced SIMD or VFP instruction is detected in the pipeline, and is disabled otherwise.

You can set bit[29] of the Auxiliary Control Register, ACTLR, to 1 to disable dynamic clock gating of the NEON and VFP unit. See Auxiliary Control Register.

L2 control and tag banks clock gating

The Cortex-A15 MPCore processor supports dynamic high-level clock gating of the shared L2 control logic and the four L2 tag banks to reduce dynamic power dissipation.

The L2 tag bank clocks are only enabled when a corresponding access is detected in the pipeline.

The L2 control logic is disabled after 256 consecutive idle cycles. It is then enabled when an L2 access is detected, with an additional 4-cycle penalty for the wake up before the access is serviced.

You can set bit[28] of the L2 Auxiliary Control Register, L2ACTLR, to 1 to disable dynamic clock gating of the L2 tag banks. See L2 Auxiliary Control Register.

You can set bit[27] of the L2 Auxiliary Control Register, L2ACTLR, to 1 to disable dynamic clock gating of the L2 control logic. See L2 Auxiliary Control Register.

Regional clock gating

Note

This feature is not available in revisions prior to r3p0.

In addition to extensive local clock gating to register flops, you can configure the Cortex-A15 MPCore processor to include regional clock gates that can perform additional clock gating of logic blocks such as the register banks. This can potentially reduce dynamic power dissipation.

You can set bit[31] of the ACTLR2 to 1 to enable regional clock gating for each processor. See Auxiliary Control Register 2.

You can set bit[26] of the L2ACTLR to 1 to enable regional clock gating in the L2, Interrupt Controller, and Timer. See L2 Auxiliary Control Register.

At reset, both of these bits are clear and the regional clock gates enables are tied HIGH. You must set these bits to 1 to enable additional clock gating in the regional clock gates for potentially reduced dynamic power dissipation.

Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412