Cortex-M4 Technical Reference Manual

Revision r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the processor
1.2. Features
1.3. Interfaces
1.4. Configurable options
1.5. Product documentation
1.5.1. Documentation
1.5.2. Design Flow
1.5.3. Architecture and protocol information
2. Functional Description
2.1. About the functions
2.2. Interfaces
2.2.1. Bus interfaces
2.2.2. ETM interface
2.2.3. AHB Trace Macrocell interface
2.2.4. Debug port AHB-AP interface
3. Programmers Model
3.1. About the programmers model
3.2. Modes of operation and execution
3.2.1. Operating modes
3.2.2. Operating states
3.2.3. Privileged access and user access
3.3. Instruction set summary
3.3.1. Cortex-M4 instructions
3.3.2. Load/store timings
3.3.3. Binary compatibility with other Cortex processors
3.4. System address map
3.4.1. Private peripheral bus
3.4.2. Unaligned accesses that cross regions
3.5. Write buffer
3.6. Exclusive monitor
3.7. Bit-banding
3.7.1. Directly accessing an alias region
3.7.2. Directly accessing a bit-band region
3.8. Processor core register summary
3.9. Exceptions
3.9.1. Exception handling
4. System Control
4.1. About system control
4.2. Register summary
4.3. Register descriptions
4.3.1. Auxiliary Control Register, ACTLR
4.3.2. CPUID Base Register, CPUID
4.3.3. Auxiliary Fault Status Register, AFSR
5. Memory Protection Unit
5.1. About the MPU
5.2. MPU functional description
5.3. MPU programmers model
6. Nested Vectored Interrupt Controller
6.1. About the NVIC
6.2. NVIC functional description
6.2.1. Low power modes
6.2.2. Level versus pulse interrupts
6.3. NVIC programmers model
6.3.1. Interrupt Controller Type Register, ICTR
7. Floating Point Unit
7.1. About the FPU
7.2. FPU Functional Description
7.2.1. FPU views of the register bank
7.2.2. Modes of operation
7.2.3. FPU instruction set
7.2.4. Compliance with the IEEE 754 standard
7.2.5. Complete implementation of the IEEE 754 standard
7.2.6. IEEE 754 standard implementation choices
7.2.7. Exceptions
7.3. FPU Programmers Model
7.3.1. Enabling the FPU
8. Debug
8.1. About debug
8.1.1. Cortex-M4 ROM table identification and entries
8.1.2. System Control Space
8.1.3. Debug register summary
8.2. About the AHB-AP
8.2.1. AHB-AP transaction types
8.2.2. AHB-AP programmers model
8.3. About the Flash Patch and Breakpoint Unit (FPB)
8.3.1. FPB functional description
8.3.2. FPB programmers model
9. Data Watchpoint and Trace Unit
9.1. About the DWT
9.2. DWT functional description
9.3. DWT Programmers Model
10. Instrumentation Trace Macrocell Unit
10.1. About the ITM
10.2. ITM functional description
10.3. ITM programmers model
10.3.1. ITM Trace Privilege Register, ITM_TPR
11. Trace Port Interface Unit
11.1. About the Cortex-M4 TPIU
11.2. TPIU functional description
11.2.1. TPIU block diagrams
11.2.2. TPIU Formatter
11.2.3. Serial Wire Output format
11.3. TPIU programmers model
11.3.1. Asynchronous Clock Prescaler Register, TPIU_ACPR
11.3.2. Formatter and Flush Status Register, TPIU_FFSR
11.3.3. Formatter and Flush Control Register, TPIU_FFCR
11.3.4. TRIGGER
11.3.5. Integration ETM Data
11.3.6. ITATBCTR2
11.3.7. Integration ITM Data
11.3.8. ITATBCTR0
11.3.9. Integration Mode Control, TPIU_ITCTRL
11.3.10. TPIU_DEVID
A. Revisions
Glossary

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Product Status

The information in this document is Final (information on a developed product).

Revision History
Revision A22 December 2009First release for r0p0
Revision B02 March 2010Second release for r0p0
Copyright © 2009, 2010 ARM Limited. All rights reserved.ARM DDI 0439B
Non-Confidential