A.1.12. Test interface signals

Table A.12 shows the test interface signals.

Table A.12. Test interface signals

Signal nameTypeDescription
DFTTESTMODEInputTest mode. This signal is used to force the STM clock on in test mode.
DFTCLKDISABLEInputTest clock disable. This signal is used to switch off the STM clock in capture phase of DFT test of other components in the system.

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