1.6. Test features

The STM includes clock gating circuitry to save power when the STM is disabled. Two Design For Test (DFT) ports are included, so that:

The DFT ports are:

DFTTESTMODE

Forces the STM clock on during DFT shift.

DFTCLKDISABLE

Can be used to shut down the STM clock during testing of other components in the system.

Note

The clock enables are directly controllable during test mode. You can turn the clocks off during test instead of forcing the clock enables on, to save power during testing.

Copyright © 2010 ARM. All rights reserved.ARM DDI 0444A
Non-ConfidentialID090310