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| Non-Confidential | ID090310 |
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The STM includes clock gating circuitry to save power when the STM is disabled. Two Design For Test (DFT) ports are included, so that:
the clock can be enabled during test of the STM
the STM clock can be disabled during test of other components in the system, to save power.
The DFT ports are:
Forces the STM clock on during DFT shift.
Can be used to shut down the STM clock during testing of other components in the system.
The clock enables are directly controllable during test mode. You can turn the clocks off during test instead of forcing the clock enables on, to save power during testing.
| Copyright © 2010 ARM. All rights reserved. | ARM DDI 0444A |
| Non-Confidential | ID090310 |
| PDF version | |
| Home > Introduction > Test features |