1.5. Configurable options

You can configure the depths of the STM FIFO buffers to match the instrumentation usage model. Deeper buffers improve STM performance, but increase area and power consumption.

Each data FIFO entry can store one 32-bit word of data and up to 16 bits of timestamp. Each channel FIFO entry can store one channel or master change message. It is not usually necessary to implement as many channel FIFO entries as data FIFO entries, because the channel or master does not usually change on every write to the AXI slave.

You can also define the presence of the hardware event observation interface and the width of AXI ID. Table 1.1 shows the configurable options.

Table 1.1. STM configurable options

Configurable option Valid valuesDescription
DATA_FIFO_DEPTH4, 8, 16, 32Depth of data FIFO buffer
CHN_FIFO_DEPTH4, 8, 16, 32[a]Depth of channel FIFO buffer
HWEVOBIF_PRESENTFALSEHardware event observation interface not present
TRUEHardware event observation interface present
AXI_ID_WIDTH2-24Width of AXI IDs, including AWID, WID, BID, ARID, and RID

[a] This value must not be more than the DATA_FIFO_DEPTH value.

If you are unsure about the instrumentation profile in your system, ARM recommends that you implement the STM in a configuration with an 8 deep channel FIFO buffer and a 16 deep data FIFO buffer.

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