3.2. Register summary

Table 3.1 shows the registers in base offset order.

Table 3.1. STM register summary

Offset

Name

Type

Reset

Description

0xC04STMDMASTARTRWO-System Trace Macrocell Programmers’ Model Architecture Specification
0xC08STMDMASTOPRWO-System Trace Macrocell Programmers’ Model Architecture Specification
0xC0CSTMDMASTATRRO-System Trace Macrocell Programmers’ Model Architecture Specification
0xC10STMDMACTLRRW0x00000000DMA Control Register
0xCFCSTMDMAIDRRO-System Trace Macrocell Programmers’ Model Architecture Specification
0xD00STMHEERRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xD20STMHETERRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xD64STMHEMCRRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xDF4STMHEMASTRRO0x00000080Hardware Event Master Number Register
0xDF8STMHEFEAT1RRO0x00100035Hardware Event Features 1 Register
0xDFCSTMHEIDRRO0x00000001Hardware Event Features ID Register
0xE00STMSPERRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE20STMSPTERRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE60STMSPSCRRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE64STMSPMSCRRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE68STMSPOVERRIDERRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE6CSTMSPMOVERRIDERRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE70STMSPTRIGCSRRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE80STMTCSRRW0x00000004Trace Control and Status Register
0xE84STMTSSTIMRWO-System Trace Macrocell Programmers’ Model Architecture Specification
0xE8CSTMTSFREQRRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE90STMSYNCRRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xE94STMAUXCRRW0x00000000Auxiliary Control Register
0xEA0STMSPFEAT1RRO0x006587D1STM Features 1 Register
0xEA4STMSPFEAT2RRO0x000104F2STM Features 2 Register
0xEA8STMSPFEAT3RRO0x0000007FSTM Features 3 Register
0xEE8STMITTRIGGERWO-Integration Test for Cross-Trigger Outputs Register
0xEECSTMITATBDATA0WO-Integration Mode ATB Data 0 Register
0xEF0STMITATBCTR2RO-Integration Mode ATB Control 2 Register
0xEF4STMITATBIDWO-Integration Mode ATB Identification Register
0xEF8STMITATBCTR0WO-Integration Mode ATB Control 0 Register
0xF00STMITCTRLRW0x00000000Integration Mode Control Register
0xFA0STMCLAIMSETRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xFA4STMCLAIMCLRRW-System Trace Macrocell Programmers’ Model Architecture Specification
0xFB0STMLARWO-Lock Access Register
0xFB4STMLSRRO[a]Lock Status Register
0xFB8STMAUTHSTATUSRO0x000000AAAuthentication Status Register
0xFC8STMDEVIDRO0x00010000Device Configuration Register
0xFCCSTMDEVTYPERO0x00000063Device Type Identifier Register
0xFE0STMPIDR0RO0x00000062Peripheral ID0 Register
0xFE4STMPIDR1RO0x000000B9Peripheral ID1 Register
0xFE8STMPIDR2RO0x0000000BPeripheral ID2 Register
0xFECSTMPIDR3RO0x00000000Peripheral ID3 Register
0xFD0STMPIDR4RO0x00000004Peripheral ID4 Register
0xFF0STMCIDR0RO0x0000000DComponent ID0 Register
0xFF4STMCIDR1RO0x00000090Component ID1 Register
0xFF8STMCIDR2RO0x00000005Component ID2 Register
0xFFCSTMCIDR3RO0x000000B1Component ID3 Register

[a] This value depends on whether you are reading the register with PADDRDBG31 HIGH or LOW.


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