| Copyright © 2010 ARM. All rights reserved. | ARM DDI 0444A |
| Non-Confidential | ID090310 |
 PDF version | |
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Table 3.1 shows the registers in base offset order.
Table 3.1. STM register summary
Offset | Name | Type | Reset | Description |
|---|---|---|---|---|
0xC04 | STMDMASTARTR | WO | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xC08 | STMDMASTOPR | WO | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xC0C | STMDMASTATR | RO | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xC10 | STMDMACTLR | RW | 0x00000000 | DMA Control Register |
0xCFC | STMDMAIDR | RO | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xD00 | STMHEER | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xD20 | STMHETER | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xD64 | STMHEMCR | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xDF4 | STMHEMASTR | RO | 0x00000080 | Hardware Event Master Number Register |
0xDF8 | STMHEFEAT1R | RO | 0x00100035 | Hardware Event Features 1 Register |
0xDFC | STMHEIDR | RO | 0x00000001 | Hardware Event Features ID Register |
0xE00 | STMSPER | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE20 | STMSPTER | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE60 | STMSPSCR | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE64 | STMSPMSCR | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE68 | STMSPOVERRIDER | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE6C | STMSPMOVERRIDER | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE70 | STMSPTRIGCSR | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE80 | STMTCSR | RW | 0x00000004 | Trace Control and Status Register |
0xE84 | STMTSSTIMR | WO | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE8C | STMTSFREQR | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE90 | STMSYNCR | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xE94 | STMAUXCR | RW | 0x00000000 | Auxiliary Control Register |
0xEA0 | STMSPFEAT1R | RO | 0x006587D1 | STM Features 1 Register |
0xEA4 | STMSPFEAT2R | RO | 0x000104F2 | STM Features 2 Register |
0xEA8 | STMSPFEAT3R | RO | 0x0000007F | STM Features 3 Register |
0xEE8 | STMITTRIGGER | WO | - | Integration Test for Cross-Trigger Outputs Register |
0xEEC | STMITATBDATA0 | WO | - | Integration Mode ATB Data 0 Register |
0xEF0 | STMITATBCTR2 | RO | - | Integration Mode ATB Control 2 Register |
0xEF4 | STMITATBID | WO | - | Integration Mode ATB Identification Register |
0xEF8 | STMITATBCTR0 | WO | - | Integration Mode ATB Control 0 Register |
0xF00 | STMITCTRL | RW | 0x00000000 | Integration Mode Control Register |
0xFA0 | STMCLAIMSET | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xFA4 | STMCLAIMCLR | RW | - | System Trace Macrocell Programmers’ Model Architecture Specification |
0xFB0 | STMLAR | WO | - | Lock Access Register |
0xFB4 | STMLSR | RO | [a] | Lock Status Register |
0xFB8 | STMAUTHSTATUS | RO | 0x000000AA | Authentication Status Register |
0xFC8 | STMDEVID | RO | 0x00010000 | Device Configuration Register |
0xFCC | STMDEVTYPE | RO | 0x00000063 | Device Type Identifier Register |
0xFE0 | STMPIDR0 | RO | 0x00000062 | Peripheral ID0 Register |
0xFE4 | STMPIDR1 | RO | 0x000000B9 | Peripheral ID1 Register |
0xFE8 | STMPIDR2 | RO | 0x0000000B | Peripheral ID2 Register |
0xFEC | STMPIDR3 | RO | 0x00000000 | Peripheral ID3 Register |
0xFD0 | STMPIDR4 | RO | 0x00000004 | Peripheral ID4 Register |
0xFF0 | STMCIDR0 | RO | 0x0000000D | Component ID0 Register |
0xFF4 | STMCIDR1 | RO | 0x00000090 | Component ID1 Register |
0xFF8 | STMCIDR2 | RO | 0x00000005 | Component ID2 Register |
0xFFC | STMCIDR3 | RO | 0x000000B1 | Component ID3 Register |
[a] This value depends on whether you are reading the register with PADDRDBG31 HIGH or LOW. | ||||
| Copyright © 2010 ARM. All rights reserved. | ARM DDI 0444A |
| Non-Confidential | ID090310 |
| PDF version | |
| Home > Programmers Model > Register summary |