2.11.2. ATB flush request and priority inversion

The STM acknowledges ATB flush requests by asserting an AFREADY output after all data present in STM before ATB flush request was made has been output.

The default behavior on ATB flush request is to flush AXI stimulus historical data first, and then flush historical data from hardware event tracing. When historical AXI data has been flushed, priority is temporarily inverted and hardware event tracing is given higher priority until it is flushed. This helps the flushed to complete as soon as possible, but can cause loss of invariant transactions on the AXI.

You can use the override control in the STMAUXCR to disable priority inversion during flush. If you set the STMAUXCR.PRIORINVDIS bit, the AXI stimulus port trace remains higher priority than hardware events trace during flush. This can cause the STM flush acknowledge to be prolonged because new AXI trace can be output before hardware historical data.

Copyright © 2010 ARM. All rights reserved.ARM DDI 0444A
Non-ConfidentialID090310