2.2. Interfaces

The STM interfaces are not configurable except for the AXI ID width. See the CoreSight System Trace Macrocell Implementation and Integration Manual for more information about how to connect these interfaces in a system. The STM has the following external interfaces:

AXI slave

This interface connects the STM to the system bus. This design provides a 32-bit AXI slave. See the AMBA AXI Protocol Specification for more information on the AXI signals.

This interface occupies space in the memory map which can be written to, to generate trace.

Hardware event observation interface

This interface consists of 32 input signals, and connects to various signals from the system, such as interrupt lines, DMA request lines, and Cross-Trigger Interface (CTI) trigger outputs.

Hardware events on this interface are captured and trace is generated based on captured events. See Hardware event tracing for more information.

DMA peripheral request interface

This interface connects to an AMBA DMA Controller DMA-330. When the STM is programmed to initiate a DMA transfer, this interface requests the DMA controller to write to the STM AXI. See DMA control for more information.

Debug APB slave interface

This interface provides access to the STM configuration and status registers.

See the AMBA APB Protocol Specification and the CoreSight Architecture Specification for more information on the debug APB signals.

ATB master interface

This is the interface for trace output. It also provides handshaking signals for making flush requests to the STM. The interface width is 32 bits.

See the AMBA ATB Protocol Specification for more information on the ATB signals.

External synchronization request

This is the interface for outputting synchronization requests to the STM.

Timestamp port interface

This interface provides the timestamp that is used in timestamped trace packets. Timestamp can be encoded as natural binary or Gray code encoding:

  • Timestamp encoding is defined by the state of TSNATURAL input. TSNATURAL must be tied off at implementation.

  • The maximum timestamp widths supported are 48 and 64 bits. The maximum output timestamp width is defined by the state of the TSMAXWIDTH configuration input. TSMAXWIDTH must be tied off at implementation.

Authentication interface

This interface provides connections for the CoreSight Authentication Interface.

The STM is a non-invasive debug component because it generates trace only in response to writes to its stimulus ports. See Extended stimulus port interface for more information.

Non-secure guaranteed stimulus port accesses enable interface

This interface provides control over behavior of non-secure guaranteed accesses to the extended stimulus ports. See Extended stimulus port interface for more information.

Cross-trigger interface

Three trigger output ports, TRIGOUTSPTE, TRIGOUTSW, and TRIGOUTHETE, are implemented to connect to a cross-trigger interface in a CoreSight system, to indicate trigger events. These correspond to the dedicated trigger outputs described in the System Trace Macrocell Programmers’ Model Architecture Specification.

The ASYNCOUT output port indicates that alignment synchronization has occurred. This can be used to generate other forms of periodic synchronisation, for example by causing an interrupt on a processor. This signal must also be connected to a cross-trigger interface input.

External synchronization interface

The SYNCREQ input port enables an external component to control the frequency of periodic synchronisation. This signal is provided for compatibility with future architectures and can be tied LOW in most designs.

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