2.3.1. Clock

The STM has a single clock input, CLK, which is synchronous to the system bus clock. You must use asynchronous bridges when connecting the STM interfaces to differently-clocked buses.

The APB interface provides a PCLKENDBG clock enable input to enable you to connect the STM to APB masters running on a slower APB clock that is an integer division of the STM CLK.

To minimize power consumption when not enabled, the STM implements architectural clock gating. The STM internal clock is gated for all parts of design except for the AXI and DMA peripheral request interfaces. These must be able to respond to transactions from the system interconnect and the DMA controller.

The architectural clock gating is transparent to the programmer. The internal clock is enabled when the STM registers are accessed or when tracing is enabled. Because the architectural clock gating is present, you do not have to gate the clock at STM block level.

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