2.1. About the functions

Figure 2.1 shows the main functional blocks of the STM.

Figure 2.1. STM block diagram

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The STM implements tracing of software writes to its stimulus ports using the AXI and tracing of hardware events.

The selection of which stimulus ports and which hardware events are traced is based on programmed controls and the state of the authentication interface.

Traced transactions from the two interfaces, AXI and hardware, are arbitrated with higher priority being assigned to AXI transactions. Trace data is then presented to the packet generation logic where it is timestamped and organized according to the STPv2 protocol.

STPv2 data is packed into the trace stream and is output on ATB interface.In case of overflow, that is, when the STM FIFO is full, the STM can either stall the AXI or drop data with overflow indicated in the trace stream. There is no stall mechanism on the hardware interface. Hardware events can either be silently dropped or an overflow condition is indicated in the trace stream.

The STM periodically outputs a synchronization sequence to enable the trace receiver to align on the packet boundary in the trace stream.

Copyright © 2010 ARM. All rights reserved.ARM DDI 0444A
Non-ConfidentialID090310