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The STMDMACTLR Register characteristics are:
Controls the DMA transfer request mechanism.
There are no usage constraints.
This register is available in all configurations.
0xC10
RW
0x00000000
32
Figure 3.1 shows the STMDMACTLR Register bit assignments.
Table 3.2 shows the STMDMACTLR Register bit assignments.
Table 3.2. STMDMACTLR Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:4] | Reserved | Reserved. |
| [3:2] | SENS | Determines the sensitivity of the DMA request to the current buffer level in the STM: b00 = Buffer is <25% b01 = Buffer is <50% b10 = Buffer is <75% full b11 = Buffer is <100% full. |
| [1:0] | Reserved | Reserved. |