3.3.1. DMA Control Register

The STMDMACTLR Register characteristics are:

Purpose

Controls the DMA transfer request mechanism.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes
Offset

0xC10

Type

RW

Reset

0x00000000

Width

32

Figure 3.1 shows the STMDMACTLR Register bit assignments.

Figure 3.1. STMDMACTLR Register bit assignments

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Table 3.2 shows the STMDMACTLR Register bit assignments.

Table 3.2. STMDMACTLR Register bit assignments

BitsNameFunction
[31:4]Reserved

Reserved.

[3:2]SENS

Determines the sensitivity of the DMA request to the current buffer level in the STM:

b00 = Buffer is <25%

b01 = Buffer is <50%

b10 = Buffer is <75% full

b11 = Buffer is <100% full.

[1:0]Reserved

Reserved.


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