3.3.2. Hardware Event Master Number Register

The STMHEMASTR Register characteristics are:

Purpose

Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes
Offset

0xDF4

Type

RO

Reset

0x00000080

Width

32

Figure 3.2 shows the STMHEMASTR Register bit assignments.

Figure 3.2. STMHEMASTR Register bit assignments

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Table 3.3 shows the STMHEMASTR Register bit assignments.

Table 3.3. STMHEMASTR Register bit assignments

BitsNameFunction
[31:16]Reserved

Reserved.

[15:0]MASTER

The STPv2 master number for hardware event trace:

0x80 = Hardware events are associated with master 0x80.


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