3.3.3. Hardware Event Features 1 Register

The STMHEFEAT1R Register characteristics are:

Purpose

Indicates the features of the STM.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes
Offset

0xDF8

Type

RO

Reset

0x00100035

Width

32

Figure 3.3 shows the STMHEFEAT1R Register bit assignments.

Figure 3.3. STMHEFEAT1R Register bit assignments

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Table 3.4 shows the STMHEFEAT1R Register bit assignments.

Table 3.4. STMHEFEAT1R Register bit assignments

BitsNameFunction
[31:24]Reserved

Reserved.

[23:15]NUMHE

The number of hardware events supported by the STM:

b000100000 = 32 hardware events.

[14:6]Reserved

Reserved.

[5:4]HECOMP

Data compression on hardware event tracing support:

b11 = Data compression support is programmable. STMHEMCR.COMPEN is implemented.

[3]HEMASTR

STMHEMASTR support:

b0 = STMHEMASTR is read-only.

[2]HEERR

Hardware event error detection support:

b1 = Hardware event error detection implemented. STMHEMCR.ERRDETECT is implemented.

[1]Reserved

Reserved.

[0]HETER

STMHETER support:

b1 = STMHETER is implemented.


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