3.3.5. Trace Control and Status Register

The STMTCSR Register characteristics are:

Purpose

Controls the STM settings.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes
Offset

0xE80

Type

RW

Reset

0x00000004

Width

32

Figure 3.5 shows the STMTCSR Register bit assignments.

Figure 3.5. STMTCSR Register bit assignments

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Table 3.6 shows the STMTCSR Register bit assignments.

Table 3.6. STMTCSR Register bit assignments

BitsNameFunction
[31:24]Reserved

Reserved.

[23]BUSY

STM is busy, for example the STM trace FIFO is not empty:

b0 = STM is not busy.

b1 = STM is busy.

[22:16]TRACEID

ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing.

[15:6]Reserved

Reserved.

[5]COMPEN

Compression Enable for Stimulus Ports:

b0 = Compression disabled, data transfers are transmitted at the size of the transaction.

b1 = Compression enabled, data transfers are compressed to save bandwidth.

[4:3]Reserved

Reserved.

[2]SYNCEN

STMSYNCR is implemented so this value is Read As One.

b1 = STMSYNCR implemented.

[1]TSEN

This bit controls if timestamp requests are ignored or not:

b0 = Timestamping disabled. Requests for timestamp generation are ignored, and stimulus port writes selecting timestamping are treated as if it were not selected.

b1 = Timestamping enabled. If stimulus writes select timestamping, a timestamp is output according to STPv2.

[0]EN

Global STM enable:

b0 = STM disabled

b1 = STM enabled.


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