3.3.6. Auxiliary Control Register

The STMAUXCR Register characteristics are:

Purpose

Used for implementation defined STM controls.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes
Offset

0xE94

Type

RW

Reset

0x00000000

Width

32

Figure 3.6 shows the STMAUXCR Register bit assignments.

Figure 3.6. STMAUXCR Register bit assignments

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Table 3.7 shows the STMAUXCR Register bit assignments.

Table 3.7. STMAUXCR Register bit assignments

BitsNameFunction
[31:5]Reserved

Reserved.

[4]AFREADYHIGH

Provides override control for the AFREADY output:

b0 = No override, AFREADY is controlled by the state of STM

b1 = Override, AFREADY is driven HIGH.

Reset value is b0.

[3]CLKON

Provides override control for architectural clock gate enable:

b0 = No override, clock gate is controlled by the state of STM

b1 = Override, clock is enabled.

Reset value is b0.

[2]PRIORINVDIS

Controls arbitration between AXI and HW during flush:

b0 = Priority inversion, when AXI flush is finished, HW gets priority until HW flush is done

b1 = Priority inversion disabled, AXI always has priority over HW.

Reset value is b0.

[1]ASYNCPE

ASYNC priority:

b0 = ASYNC priority is always lower than trace.

b1 = ASYNC priority escalates on second synchronization request.

Reset value is b0.

[0]FIFOAF

Auto-flush:

b0 = Auto-flush disabled.

b1 = Auto-flush enabled. The STM automatically drains all data it has even if the ATB interface is not fully utilized.

Reset value is b0.


ARM recommends that you leave the STMAUXCR Register at its default reset value.

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