3.3.7. STM Features 1 Register

The STMSPFEAT1R Register characteristics are:

Purpose

Indicates the features of the STM.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes
Offset

0xEA0

Type

RO

Reset

0x006587D1

Width

32

Figure 3.7 shows the STMSPFEAT1R Register bit assignments.

Figure 3.7. STMSPFEAT1R Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.8 shows the STMSPFEAT1R Register bit assignments.

Table 3.8. STMSPFEAT1R Register bit assignments

BitsNameFunction
[31:24]Reserved

Reserved.

[23:22]SWOEN

STMTCSR.SWOEN support:

b01 = STMTCSR.SWOEN not implemented.

[21:20]SYNCEN

STMTCSR.SYNCEN support:

b10 = STMTCSR.SYNCEN implemented but always reads as b1.

[19:18]HWTEN

STMTCSR.HWTEN support:

b01 = STMTCSR.HWTEN not implemented.

[17:16]TSPRESCALE

Timestamp prescale support:

b01 = Timestamp prescale not implemented.

[15:14]TRIGCTL

Trigger control support:

b10 = Multi-shot and single-shot triggers supported. STMTRIGCSR implemented.

[13:10]TRACEBUS

Trace bus support:

b0001 = CoreSight ATB plus ATB trigger support implemented. STMTCSR.TRACEID and STMTRIGCSR.ATBTRIGEN implemented.

[9:8]SYNC

STMSYNCR support:

b11 = STMSYNCR implemented with MODE control

[7]FORCETS

STMTSSTIMR support:

b1 = STMTSSTIMR bit [0] implemented.

[6]TSFREQ

Timestamp frequency indication configuration:

b1 = STMTSFREQR is read-write.

[5:4]TS

Timestamp support:

b01 = Absolute timestamps implemented.

[3:0]PROT

Protocol:

b0001 = STPv2 protocol


Copyright © 2010 ARM. All rights reserved.ARM DDI 0444A
Non-ConfidentialID090310