3.3.8. STM Features 2 Register

The STMSPFEAT2R Register characteristics are:

Purpose

Indicates the features of the STM.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes
Offset

0xEA4

Type

RO

Reset

0x000104F2

Width

32

Figure 3.8 shows the STMSPFEAT2R Register bit assignments.

Figure 3.8. STMSPFEAT2R Register bit assignments

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Table 3.9 shows the STMSPFEAT2R Register bit assignments.

Table 3.9. STMSPFEAT2R Register bit assignments

BitsNameFunction
[31:18]Reserved

Reserved.

[17:16]SPTYPE

Stimulus port type support:

b01 = Only extended stimulus ports are implemented.

[15:12]DSIZE

Fundamental data size:

b0000 = 32-bit data.

[11]Reserved

Reserved.

[10:9]SPTRTYPE

Stimulus port transaction type support:

b10 = Both invariant timing and guaranteed transactions are supported.

[8:7]PRIVMASK

STMPRIVMASKR support:

b01 = STMPRIVMASKR not implemented.

[6]SPOVERRIDE

STMSPOVERRIDER support:

b1 = STMSPOVERRIDER and STMSPMOVERRIDER implemented.

[5:4]SPCOMP

Data compression on stimulus ports support:

b11 = Data compression support is programmable. STMTCSR.COMPEN is implemented.

[3]Reserved

Reserved.

[2]SPER

STMSPER presence:

b0 = STMSPER is implemented.

[1:0]SPTER

STMSPTER support:

b10 = STMSPTER is implemented.


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