CoreSight System Trace Macrocell Technical Reference Manual: 3.3.17. Lock Status Register

3.3.17. Lock Status Register

The STMLSR Register characteristics are:

Purpose

This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes

Offset: 0xFB4
Type: RO
Reset: 0x00000003
Width: 32

Figure 3.17 shows the STMLSR Register bit assignments.

Figure 3.17. STMLSR Register bit assignments

Table 3.18 shows the STMLSR Register bit assignments.

Table 3.18. STMLSR Register bit assignments

Bits	Name	Function
[31:3]	Reserved	Reserved.
[2]	TYPE	Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. b0 = This component implements a 32-bit Lock Access Register.
[1]	LOCKED	Returns the current status of the Lock. b0 = Write access is allowed to this device. b1 = Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted.
[0]	PRESENT	Indicates that a lock control mechanism exists for this device. b0 = No lock control mechanism exists, writes to the Lock Access Register are ignored. b1 = Lock control mechanism is present.

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