3.3.25. Peripheral ID4 Register

The STMPIDR4 Register characteristics are:

Purpose

Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes
Offset

0xFD0

Type

RO

Reset

0x00000004

Width

32

Figure 3.25 shows the STMPIDR4 Register bit assignments.

Figure 3.25. STMPIDR4 Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.26 shows the STMPIDR4 Register bit assignments.

Table 3.26. STMPIDR4 Register bit assignments

BitsNameFunction
[31:8]Reserved

Reserved.

[7:4]FourKB_Count

This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB, this must read as 0x0, 4KB only. For 8KB set to 0x1, for 16KB set to 0x2, for 32KB set to 0x3, and so on.

0x0 = Indicates that the device only occupies 4KB of memory.

[3:0]JEP106_cont

JEDEC continuation code indicating the designer of the component, together with the identity code.

0x4 = Indicates that ARM's JEDEC identity code is on the 5th bank.


Copyright © 2010 ARM. All rights reserved.ARM DDI 0444A
Non-ConfidentialID090310