CoreSight™ System Trace Macrocell Technical Reference Manual

Revision: r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the System Trace Macrocell
1.2. Compliance
1.2.1. System Trace Protocol
1.2.2. System Trace Macrocell Programmers’ Model Architecture
1.2.3. CoreSight Architecture
1.2.4. Advanced Microcontroller Bus Architecture
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation, design flow, and architecture
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional Description
2.1. About the functions
2.2. Interfaces
2.3. Clocking and resets
2.3.1. Clock
2.3.2. Resets
2.4. Trace protocol
2.4.1. Trace packets
2.4.2. Alignment synchronization
2.4.3. Error packets
2.4.4. Word output
2.5. Timestamping
2.6. Triggering
2.6.1. TRIGOUT ports
2.7. Extended stimulus port interface
2.7.1. AXI responses
2.7.2. STM enabled
2.7.3. STM disabled
2.7.4. AXI reads
2.7.5. Stimulus port and trigger enables
2.7.6. Invariant-timing packets and overflow
2.8. Hardware event tracing
2.9. DMA control
2.9.1. Starting and stopping requests
2.9.2. FIFO level monitoring
2.9.3. DMA interface behavior
2.10. Data compression
2.11. Buffer flushing
2.11.1. Override using auto-flush
2.11.2. ATB flush request and priority inversion
2.11.3. ATB AFREADY override
2.12. ATB data ordering
2.13. Integration mode and topology detection
2.14. Constraints and limitations of use
3. Programmers Model
3.1. About the programmers model
3.2. Register summary
3.3. Register descriptions
3.3.1. DMA Control Register
3.3.2. Hardware Event Master Number Register
3.3.3. Hardware Event Features 1 Register
3.3.4. Hardware Event Features ID Register
3.3.5. Trace Control and Status Register
3.3.6. Auxiliary Control Register
3.3.7. STM Features 1 Register
3.3.8. STM Features 2 Register
3.3.9. STM Features 3 Register
3.3.10. Integration Test for Cross-Trigger Outputs Register
3.3.11. Integration Mode ATB Data 0 Register
3.3.12. Integration Mode ATB Control 2 Register
3.3.13. Integration Mode ATB Identification Register
3.3.14. Integration Mode ATB Control 0 Register
3.3.15. Integration Mode Control Register
3.3.16. Lock Access Register
3.3.17. Lock Status Register
3.3.18. Authentication Status Register
3.3.19. Device Configuration Register
3.3.20. Device Type Identifier Register
3.3.21. Peripheral ID0 Register
3.3.22. Peripheral ID1 Register
3.3.23. Peripheral ID2 Register
3.3.24. Peripheral ID3 Register
3.3.25. Peripheral ID4 Register
3.3.26. Component ID0 Register
3.3.27. Component ID1 Register
3.3.28. Component ID2 Register
3.3.29. Component ID3 Register
A. Signal Descriptions
A.1. Signal descriptions
A.1.1. Clocks and resets
A.1.2. AXI slave
A.1.3. Debug APB interface
A.1.4. ATB master interface
A.1.5. Hardware event observation interface signals
A.1.6. DMA peripheral request interface signals
A.1.7. Timestamp port signals
A.1.8. Authentication interface signals
A.1.9. Non-secure guaranteed interface signals
A.1.10. Cross-trigger interface signals
A.1.11. External synchronization request interface signals
A.1.12. Test interface signals
B. Revisions
Glossary

List of Tables

1.1. STM configuration
1.2. STM configurable options
2.1. Generated trace packets
2.2. TRIGOUT ports
2.3. Supported values of WSTRBS
2.4. Authentication control with non-secure access
2.5. Authentication control with guaranteed override
2.6. ATB writes
2.7. Non-generated trace packets
3.1. STM register summary
3.2. STMDMACTLR Register bit assignments
3.3. STMHEMASTR Register bit assignments
3.4. STMHEFEAT1R Register bit assignments
3.5. STMHEIDR Register bit assignments
3.6. STMTCSR Register bit assignments
3.7. STMAUXCR Register bit assignments
3.8. STMSPFEAT1R Register bit assignments
3.9. STMSPFEAT2R Register bit assignments
3.10. STMSPFEAT3R Register bit assignments
3.11. STMITTRIGGER Register bit assignments
3.12. STMITATBDATA0 Register bit assignments
3.13. STMITATBCTR2 Register bit assignments
3.14. STMITATBID Register bit assignments
3.15. STMITATBCTR0 Register bit assignments
3.16. STMITCTRL Register bit assignments
3.17. STMLAR Register bit assignments
3.18. STMLSR Register bit assignments
3.19. STMAUTHSTATUS Register bit assignments
3.20. STMDEVID Register bit assignments
3.21. STMDEVTYPE Register bit assignments
3.22. STMPIDR0 Register bit assignments
3.23. STMPIDR1 Register bit assignments
3.24. STMPIDR2 Register bit assignments
3.25. STMPIDR3 Register bit assignments
3.26. STMPIDR4 Register bit assignments
3.27. STMCIDR0 Register bit assignments
3.28. STMCIDR1 Register bit assignments
3.29. STMCIDR2 Register bit assignments
3.30. STMCIDR3 Register bit assignments
A.1. Clock and reset signals
A.2. AXI slave signals
A.3. Debug APB interface signals
A.4. ATB master interface signals
A.5. Hardware event observation interface signals
A.6. DMA peripheral request interface
A.7. Timestamp port signals
A.8. Authentication interface signals
A.9. Non-secure guaranteed interface signals
A.10. Cross-trigger interface signals
A.11. External synchronization request interface signals
A.12. Test interface signals
B.1. Issue A
B.2. Differences between Issue A and Issue B

Proprietary Notice

Words and logos marked with or are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A23 April 2010First release for r0p0
Revision B10 December 2010First release for r0p1
Copyright © 2010 ARM. All rights reserved.ARM DDI 0444B
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