Cortex-A5 Floating-Point Unit Technical Reference ManualRevision: r0p0
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2.3.1. Processor modes for accessing the FPU system registers

Table 2.3 shows the processor modes for accessing the Cortex-A5 FPU system registers.

Table 2.3. Accessing Cortex-A5 FPU system registers

Register Privileged access User access
FPEXC EN=0FPEXC EN=1 FPEXC EN=0 FPEXC EN=1
FPSID Permitted Permitted Not permitted Not permitted
FPSCRNot permittedPermittedNot permittedPermitted
MVFR0, MVFR1Permitted Permitted Not permittedNot permitted
FPEXCPermittedPermitted Not permitted Not permitted

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