Cortex-A5 Floating-Point Unit Technical Reference Manual: 2.4.5. Floating-Point Exception Register

The FPEXC Register characteristics are:

Purpose

Provides global enable control of the VFP extension.

Usage constraints

This register is:

Only accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see VFP register access.
Only accessible in privileged modes, and only if access to coprocessors CP10 and CP11 is enabled in the CPACR, see VFP register access.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 2.2.

Figure 2.5 shows the FPEXC Register bit assignments.

Figure 2.5. FPEXC Register bit assignments

Table 2.8 shows the FPEXC Register bit assignments.

Table 2.8. FPEXC Register bit assignments

Bits	Name	Function
[31]	EX	The Cortex-A5 FPU does not generate asynchronous VFP exceptions, therefore this bit is RAZ/WI.
[30]	EN	FPU enable bit: b0 = FPU disabled. b1 = FPU enabled. The EN bit is cleared to 0 at reset.
[29]	DEX	Defined synchronous instruction exceptional flag. The Cortex-A5 FPU sets this bit when generating a synchronous bounce because of an attempt to execute a vector operation. All other Undefined Instruction exceptions clear this bit to zero. See the ARM Architecture Reference Manual for more information.
[28:0]	Reserved	RAZ/WI.

You can access the FPEXC Register with the following VMSR instructions:

VMRS <Rd>, FPEXC ; Read Floating-Point Status and Control Register

VMSR FPEXC, <Rt> ; Write Floating-Point Status and Control Register

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