Cortex-A5 Floating-Point Unit Technical Reference Manual: 2.4.3. Media and VFP Feature Register 0

The MVFR0 characteristics are:

Purpose

Together with MVFR1, describes the features that the FPU provides.

Usage constraints

This register is:

Only accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see VFP register access.
Only accessible in privileged modes, and only if access to coprocessors CP10 and CP11 is enabled in the CPACR and FPEXC.EN is set, see VFP register access.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 2.2.

Figure 2.3 shows the MVFR0 bit assignments.

Figure 2.3. MVFR0 bit assignments

Table 2.6 shows the MVFR0 bit assignments.

Table 2.6. MVFR0 bit assignments

Bits	Name	Function
[31:28]	VFP rounding modes	All VFP rounding modes supported
[27:24]	Short vectors	VFP short vectors not supported
[23:20]	Square root	VFP square root operation supported
[19:16]	Divide	VFP divide operation supported
[15:12]	VFP exception trapping	VFP exception trapping not supported
[11:8]	Double-precision	Double-precision operations supported
[7:4]	Single-precision	Single-precision operations supported
[3:0]	A_SIMD registers	Sixteen 64-bit registers supported

You can access the MVFR0 with the following VMSR instruction:

VMRS <Rd>, MVFR0 ; Read Media and VFP Feature Register 0

Copyright © 2009 ARM. All rights reserved.	ARM DDI 0449A
Non-Confidential
PDF version