Cortex-A5 Floating-Point Unit Technical Reference Manual: 2.4.1. Floating-Point System ID Register

The FPSID Register characteristics are:

Purpose

Provides information about the VFP implementation.

Usage constraints

This register is:

Only accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see VFP register access.
Only accessible in privileged modes, and only if access to coprocessors CP10 and CP11 is enabled in the CPACR and FPEXC.EN is set, see VFP register access.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 2.2.

Figure 2.1 shows the FPSID Register bit assignments.

Figure 2.1. FPSID Register bit assignments

Table 2.4 shows the FPSID Register bit assignments.

Table 2.4. FPSID Register bit assignments

Bits	Name	Function
[31:24]	Implementer	Denotes ARM. Value is `0x41`.
[23]	SW	Hardware implementation with no software emulation. Value is `0`.
[22:16]	Subarchitecture	VFPv3 or greater with v2 subarchitecture. Value is `2`.
[15:8]	Part number	Cortex-A. Value is `0x30`.
[7:4]	Variant	Cortex-A5. Value is `5`.
[3:0]	Revision	Revision. Value is `0`.

You can access the FPSID Register with the following VMRS instruction:

VMRS <Rd>, FPSID ; Read Floating-Point System ID Register

Copyright © 2009 ARM. All rights reserved.	ARM DDI 0449A
Non-Confidential
PDF version