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Table 2.2 shows the Cortex-A5 FPU system registers. All FPU system registers are 32-bit wide. Reserved register addresses are Unpredictable.
Table 2.2. Cortex-A5 FPU system registers
| Name | Type | Reset | Description |
|---|---|---|---|
| FPSID | RO | 0x41023051 | Floating-Point System ID Register |
| FPSCR | RW | 0x00000000 | Floating-Point Status and Control Register |
| MVFR0 | RO | 0x10110221 | Media and VFP Feature Register 0 |
| MVFR1 | RO | 0x11000011 | Media and VFP Feature Register 1 |
| FPEXC | RW | 0x00000000 | Floating-Point Exception Register |
The FPINST and FPINST2 registers are not implemented, and any attempt to access them is Unpredictable.
| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0449B |
| Non-Confidential | ID101810 |
| PDF version | |
| Home > Programmers Model > Register summary |